File Manager

003 File Manager

Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/AArch64

usr / src / contrib / llvm-project / llvm / lib / Target / AArch64 /

📁 ..
📄 AArch64.h(4.09 KB)
📄 AArch64.td(49.85 KB)
📄 AArch64A53Fix835769.cpp(8.3 KB)
📄 AArch64A57FPLoadBalancing.cpp(25.73 KB)
📄 AArch64AdvSIMDScalarPass.cpp(16.1 KB)
📄 AArch64AsmPrinter.cpp(49.26 KB)
📄 AArch64BranchTargets.cpp(4.91 KB)
📄 AArch64CallingConvention.cpp(6.63 KB)
📄 AArch64CallingConvention.h(2.62 KB)
📄 AArch64CallingConvention.td(23.84 KB)
📄 AArch64CleanupLocalDynamicTLSPass.cpp(5.53 KB)
📄 AArch64CollectLOH.cpp(20.07 KB)
📄 AArch64Combine.td(3.27 KB)
📄 AArch64CompressJumpTables.cpp(5.06 KB)
📄 AArch64CondBrTuning.cpp(10.19 KB)
📄 AArch64ConditionOptimizer.cpp(15.26 KB)
📄 AArch64ConditionalCompares.cpp(33.26 KB)
📄 AArch64DeadRegisterDefinitionsPass.cpp(7.76 KB)
📄 AArch64ExpandImm.cpp(14.25 KB)
📄 AArch64ExpandImm.h(959 B)
📄 AArch64ExpandPseudoInsts.cpp(38.08 KB)
📄 AArch64FalkorHWPFFix.cpp(23.3 KB)
📄 AArch64FastISel.cpp(171.76 KB)
📄 AArch64FrameLowering.cpp(124.13 KB)
📄 AArch64FrameLowering.h(5.54 KB)
📄 AArch64GenRegisterBankInfo.def(11 KB)
📄 AArch64ISelDAGToDAG.cpp(180.26 KB)
📄 AArch64ISelLowering.cpp(578.95 KB)
📄 AArch64ISelLowering.h(33.88 KB)
📄 AArch64InstrAtomics.td(20.33 KB)
📄 AArch64InstrFormats.td(430.93 KB)
📄 AArch64InstrGISel.td(4.29 KB)
📄 AArch64InstrInfo.cpp(243.23 KB)
📄 AArch64InstrInfo.h(19.92 KB)
📄 AArch64InstrInfo.td(374.84 KB)
📄 AArch64LoadStoreOptimizer.cpp(77.04 KB)
📄 AArch64MCInstLower.cpp(11.72 KB)
📄 AArch64MCInstLower.h(1.69 KB)
📄 AArch64MachineFunctionInfo.cpp(1.02 KB)
📄 AArch64MachineFunctionInfo.h(12.9 KB)
📄 AArch64MacroFusion.cpp(11.47 KB)
📄 AArch64MacroFusion.h(891 B)
📄 AArch64PBQPRegAlloc.cpp(11.35 KB)
📄 AArch64PBQPRegAlloc.h(1.3 KB)
📄 AArch64PerfectShuffle.h(382.04 KB)
📄 AArch64PfmCounters.td(713 B)
📄 AArch64PromoteConstant.cpp(22.43 KB)
📄 AArch64RedundantCopyElimination.cpp(17.09 KB)
📄 AArch64RegisterBanks.td(719 B)
📄 AArch64RegisterInfo.cpp(29.6 KB)
📄 AArch64RegisterInfo.h(5.5 KB)
📄 AArch64RegisterInfo.td(51 KB)
📄 AArch64SIMDInstrOpt.cpp(26.07 KB)
📄 AArch64SLSHardening.cpp(15.92 KB)
📄 AArch64SVEInstrInfo.td(169.43 KB)
📄 AArch64SchedA53.td(15.28 KB)
📄 AArch64SchedA57.td(34.69 KB)
📄 AArch64SchedA57WriteRes.td(19.87 KB)
📄 AArch64SchedCyclone.td(29.82 KB)
📄 AArch64SchedExynosM3.td(42.57 KB)
📄 AArch64SchedExynosM4.td(49.81 KB)
📄 AArch64SchedExynosM5.td(50.74 KB)
📄 AArch64SchedFalkor.td(5.3 KB)
📄 AArch64SchedFalkorDetails.td(67.66 KB)
📄 AArch64SchedKryo.td(6.21 KB)
📄 AArch64SchedKryoDetails.td(82.63 KB)
📄 AArch64SchedPredExynos.td(7.5 KB)
📄 AArch64SchedPredicates.td(27.86 KB)
📄 AArch64SchedThunderX.td(14.99 KB)
📄 AArch64SchedThunderX2T99.td(68.58 KB)
📄 AArch64SchedThunderX3T110.td(68.77 KB)
📄 AArch64Schedule.td(3.86 KB)
📄 AArch64SelectionDAGInfo.cpp(5.54 KB)
📄 AArch64SelectionDAGInfo.h(1.46 KB)
📄 AArch64SpeculationHardening.cpp(29.6 KB)
📄 AArch64StackOffset.h(5.01 KB)
📄 AArch64StackTagging.cpp(24.31 KB)
📄 AArch64StackTaggingPreRA.cpp(7.25 KB)
📄 AArch64StorePairSuppress.cpp(6.26 KB)
📄 AArch64Subtarget.cpp(12.38 KB)
📄 AArch64Subtarget.h(18.49 KB)
📄 AArch64SystemOperands.td(81.75 KB)
📄 AArch64TargetMachine.cpp(26.65 KB)
📄 AArch64TargetMachine.h(3.25 KB)
📄 AArch64TargetObjectFile.cpp(3.35 KB)
📄 AArch64TargetObjectFile.h(2.31 KB)
📄 AArch64TargetTransformInfo.cpp(42.6 KB)
📄 AArch64TargetTransformInfo.h(8.68 KB)
📁 AsmParser
📁 Disassembler
📁 GISel
📁 MCTargetDesc
📄 SVEInstrFormats.td(304.03 KB)
📄 SVEIntrinsicOpts.cpp(8.13 KB)
📁 TargetInfo
📁 Utils

Editing: AArch64SchedA57WriteRes.td

//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
// below is to define a generic SchedWriteRes for every combination of
// latency and microOps. The naming conventions is to use a prefix, one field
// for latency, and one or more microOp count/type designators.
//   Prefix: A57Write
//   Latency: #cyc
//   MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
//
// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
//      11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Define Generic 1 micro-op types

def A57Write_5cyc_1L  : SchedWriteRes<[A57UnitL]> { let Latency = 5;  }
def A57Write_5cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 5;  }
def A57Write_5cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 5;  }
def A57Write_5cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
                                                    let ResourceCycles = [17]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
                                                    let ResourceCycles = [19]; }
def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;  }
def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;  }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
                                                    let ResourceCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
                                                    let ResourceCycles = [35]; }
def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }
def A57Write_3cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 3;  }
def A57Write_3cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 3;  }
def A57Write_4cyc_1L  : SchedWriteRes<[A57UnitL]> { let Latency = 4;  }
def A57Write_4cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
def A57Write_9cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
def A57Write_6cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 6;  }
def A57Write_6cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 6;  }

//===----------------------------------------------------------------------===//
// Define Generic 2 micro-op types

def A57Write_64cyc_2W    : SchedWriteRes<[A57UnitW, A57UnitW]> {
  let Latency     = 64;
  let NumMicroOps = 2;
  let ResourceCycles = [32, 32];
}
def A57Write_6cyc_1I_1L  : SchedWriteRes<[A57UnitI,
                                          A57UnitL]> {
  let Latency     = 6;
  let NumMicroOps = 2;
}
def A57Write_7cyc_1V_1X  : SchedWriteRes<[A57UnitV,
                                          A57UnitX]> {
  let Latency     = 7;
  let NumMicroOps = 2;
}
def A57Write_8cyc_1L_1V  : SchedWriteRes<[A57UnitL,
                                          A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 2;
}
def A57Write_9cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 2;
}
def A57Write_8cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
  let Latency     = 8;
  let NumMicroOps = 2;
}
def A57Write_6cyc_2L     : SchedWriteRes<[A57UnitL, A57UnitL]> {
  let Latency     = 6;
  let NumMicroOps = 2;
}
def A57Write_6cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
  let Latency     = 6;
  let NumMicroOps = 2;
}
def A57Write_6cyc_2W     : SchedWriteRes<[A57UnitW, A57UnitW]> {
  let Latency     = 6;
  let NumMicroOps = 2;
}
def A57Write_5cyc_1I_1L  : SchedWriteRes<[A57UnitI,
                                          A57UnitL]> {
  let Latency     = 5;
  let NumMicroOps = 2;
}
def A57Write_5cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
  let Latency     = 5;
  let NumMicroOps = 2;
}
def A57Write_5cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
  let Latency     = 5;
  let NumMicroOps = 2;
}
def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
                                          A57UnitV]> {
  let Latency     = 10;
  let NumMicroOps = 2;
}
def A57Write_10cyc_2V    : SchedWriteRes<[A57UnitV, A57UnitV]> {
  let Latency     = 10;
  let NumMicroOps = 2;
}
def A57Write_1cyc_1B_1I  : SchedWriteRes<[A57UnitB,
                                          A57UnitI]> {
  let Latency     = 1;
  let NumMicroOps = 2;
}
def A57Write_1cyc_1I_1S  : SchedWriteRes<[A57UnitI,
                                          A57UnitS]> {
  let Latency     = 1;
  let NumMicroOps = 2;
}
def A57Write_2cyc_1B_1I  : SchedWriteRes<[A57UnitB,
                                          A57UnitI]> {
  let Latency     = 2;
  let NumMicroOps = 2;
}
def A57Write_2cyc_2S     : SchedWriteRes<[A57UnitS, A57UnitS]> {
  let Latency     = 2;
  let NumMicroOps = 2;
}
def A57Write_2cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
  let Latency     = 2;
  let NumMicroOps = 2;
}
def A57Write_34cyc_2W    : SchedWriteRes<[A57UnitW, A57UnitW]> {
  let Latency     = 34;
  let NumMicroOps = 2;
  let ResourceCycles = [17, 17];
}
def A57Write_3cyc_1I_1M  : SchedWriteRes<[A57UnitI,
                                          A57UnitM]> {
  let Latency     = 3;
  let NumMicroOps = 2;
}
def A57Write_3cyc_1I_1S  : SchedWriteRes<[A57UnitI,
                                          A57UnitS]> {
  let Latency     = 3;
  let NumMicroOps = 2;
}
def A57Write_3cyc_1S_1V  : SchedWriteRes<[A57UnitS,
                                          A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 2;
}
def A57Write_3cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 2;
}
def A57Write_4cyc_1I_1L  : SchedWriteRes<[A57UnitI,
                                          A57UnitL]> {
  let Latency     = 4;
  let NumMicroOps = 2;
}
def A57Write_4cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
  let Latency     = 4;
  let NumMicroOps = 2;
}

//===----------------------------------------------------------------------===//
// Define Generic 3 micro-op types

def A57Write_10cyc_3V       : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 10;
  let NumMicroOps = 3;
}
def A57Write_2cyc_1I_2S     : SchedWriteRes<[A57UnitI,
                                             A57UnitS, A57UnitS]> {
  let Latency     = 2;
  let NumMicroOps = 3;
}
def A57Write_3cyc_1I_1S_1V  : SchedWriteRes<[A57UnitI,
                                             A57UnitS,
                                             A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 3;
}
def A57Write_3cyc_1M_2S     : SchedWriteRes<[A57UnitM,
                                             A57UnitS, A57UnitS]> {
  let Latency     = 3;
  let NumMicroOps = 3;
}
def A57Write_3cyc_3S        : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> {
  let Latency     = 3;
  let NumMicroOps = 3;
}
def A57Write_3cyc_2S_1V     : SchedWriteRes<[A57UnitS, A57UnitS,
                                             A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 3;
}
def A57Write_5cyc_1I_2L     : SchedWriteRes<[A57UnitI,
                                             A57UnitL, A57UnitL]> {
  let Latency     = 5;
  let NumMicroOps = 3;
}
def A57Write_6cyc_1I_2L     : SchedWriteRes<[A57UnitI,
                                             A57UnitL, A57UnitL]> {
  let Latency     = 6;
  let NumMicroOps = 3;
}
def A57Write_6cyc_3V        : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 6;
  let NumMicroOps = 3;
}
def A57Write_7cyc_3L        : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> {
  let Latency     = 7;
  let NumMicroOps = 3;
}
def A57Write_8cyc_1I_1L_1V  : SchedWriteRes<[A57UnitI,
                                             A57UnitL,
                                             A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 3;
}
def A57Write_8cyc_1L_2V     : SchedWriteRes<[A57UnitL,
                                             A57UnitV, A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 3;
}
def A57Write_8cyc_3V        : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 3;
}
def A57Write_9cyc_3V        : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 3;
}

//===----------------------------------------------------------------------===//
// Define Generic 4 micro-op types

def A57Write_2cyc_2I_2S    : SchedWriteRes<[A57UnitI, A57UnitI,
                                            A57UnitS, A57UnitS]> {
  let Latency     = 2;
  let NumMicroOps = 4;
}
def A57Write_3cyc_2I_2S    : SchedWriteRes<[A57UnitI, A57UnitI,
                                            A57UnitS, A57UnitS]> {
  let Latency     = 3;
  let NumMicroOps = 4;
}
def A57Write_3cyc_1I_3S    : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS, A57UnitS]> {
  let Latency     = 3;
  let NumMicroOps = 4;
}
def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS,
                                            A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 4;
}
def A57Write_4cyc_4S       : SchedWriteRes<[A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS]> {
  let Latency     = 4;
  let NumMicroOps = 4;
}
def A57Write_7cyc_1I_3L    : SchedWriteRes<[A57UnitI,
                                            A57UnitL, A57UnitL, A57UnitL]> {
  let Latency     = 7;
  let NumMicroOps = 4;
}
def A57Write_5cyc_2I_2L    : SchedWriteRes<[A57UnitI, A57UnitI,
                                            A57UnitL, A57UnitL]> {
  let Latency     = 5;
  let NumMicroOps = 4;
}
def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI,
                                            A57UnitL,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 4;
}
def A57Write_8cyc_4L       : SchedWriteRes<[A57UnitL, A57UnitL,
                                            A57UnitL, A57UnitL]> {
  let Latency     = 8;
  let NumMicroOps = 4;
}
def A57Write_9cyc_2L_2V    : SchedWriteRes<[A57UnitL, A57UnitL,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 4;
}
def A57Write_9cyc_1L_3V    : SchedWriteRes<[A57UnitL,
                                            A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 4;
}
def A57Write_12cyc_4V      : SchedWriteRes<[A57UnitV, A57UnitV,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 12;
  let NumMicroOps = 4;
}

//===----------------------------------------------------------------------===//
// Define Generic 5 micro-op types

def A57Write_3cyc_3S_2V    : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 5;
}
def A57Write_8cyc_1I_4L    : SchedWriteRes<[A57UnitI,
                                            A57UnitL, A57UnitL,
                                            A57UnitL, A57UnitL]> {
  let Latency     = 8;
  let NumMicroOps = 5;
}
def A57Write_4cyc_1I_4S    : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS]> {
  let Latency     = 4;
  let NumMicroOps = 5;
}
def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI,
                                            A57UnitL, A57UnitL,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 5;
}
def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI,
                                            A57UnitL,
                                            A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 5;
}
def A57Write_9cyc_2L_3V    : SchedWriteRes<[A57UnitL, A57UnitL,
                                            A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 5;
}
def A57Write_9cyc_5V       : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 5;
}

//===----------------------------------------------------------------------===//
// Define Generic 6 micro-op types

def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 3;
  let NumMicroOps = 6;
}
def A57Write_4cyc_2I_4S    : SchedWriteRes<[A57UnitI, A57UnitI,
                                            A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS]> {
  let Latency     = 4;
  let NumMicroOps = 6;
}
def A57Write_4cyc_4S_2V    : SchedWriteRes<[A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 4;
  let NumMicroOps = 6;
}
def A57Write_6cyc_6S       : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS, A57UnitS]> {
  let Latency     = 6;
  let NumMicroOps = 6;
}
def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI,
                                            A57UnitL, A57UnitL,
                                            A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 6;
}
def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI,
                                            A57UnitL,
                                            A57UnitV, A57UnitV,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 6;
}
def A57Write_9cyc_2L_4V    : SchedWriteRes<[A57UnitL, A57UnitL,
                                            A57UnitV, A57UnitV,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 6;
}

//===----------------------------------------------------------------------===//
// Define Generic 7 micro-op types

def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL,
                                          A57UnitV, A57UnitV,
                                          A57UnitV, A57UnitV]> {
  let Latency     = 10;
  let NumMicroOps = 7;
}
def A57Write_4cyc_1I_4S_2V  : SchedWriteRes<[A57UnitI,
                                             A57UnitS, A57UnitS,
                                             A57UnitS, A57UnitS,
                                             A57UnitV, A57UnitV]> {
  let Latency     = 4;
  let NumMicroOps = 7;
}
def A57Write_6cyc_1I_6S     : SchedWriteRes<[A57UnitI,
                                          A57UnitS, A57UnitS, A57UnitS,
                                          A57UnitS, A57UnitS, A57UnitS]> {
  let Latency     = 6;
  let NumMicroOps = 7;
}
def A57Write_9cyc_1I_2L_4V  : SchedWriteRes<[A57UnitI,
                                             A57UnitL, A57UnitL,
                                             A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV]> {
  let Latency     = 9;
  let NumMicroOps = 7;
}
def A57Write_12cyc_7V       : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV]> {
  let Latency     = 12;
  let NumMicroOps = 7;
}

//===----------------------------------------------------------------------===//
// Define Generic 8 micro-op types

def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
                                             A57UnitL, A57UnitL, A57UnitL,
                                             A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV]> {
  let Latency     = 10;
  let NumMicroOps = 8;
}
def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
                                          A57UnitL, A57UnitL,
                                          A57UnitV, A57UnitV,
                                          A57UnitV, A57UnitV]> {
  let Latency     = 11;
  let NumMicroOps = 8;
}
def A57Write_8cyc_8S  : SchedWriteRes<[A57UnitS, A57UnitS,
                                       A57UnitS, A57UnitS,
                                       A57UnitS, A57UnitS,
                                       A57UnitS, A57UnitS]> {
  let Latency     = 8;
  let NumMicroOps = 8;
}

//===----------------------------------------------------------------------===//
// Define Generic 9 micro-op types

def A57Write_8cyc_1I_8S     : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS]> {
  let Latency     = 8;
  let NumMicroOps = 9;
}
def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
                                             A57UnitL, A57UnitL,
                                             A57UnitL, A57UnitL,
                                             A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV]> {
  let Latency     = 11;
  let NumMicroOps = 9;
}
def A57Write_15cyc_9V       : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV, A57UnitV,
                                             A57UnitV, A57UnitV, A57UnitV]> {
  let Latency     = 15;
  let NumMicroOps = 9;
}

//===----------------------------------------------------------------------===//
// Define Generic 10 micro-op types

def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
                                         A57UnitS, A57UnitS, A57UnitS,
                                         A57UnitV, A57UnitV,
                                         A57UnitV, A57UnitV]> {
  let Latency     = 6;
  let NumMicroOps = 10;
}

//===----------------------------------------------------------------------===//
// Define Generic 11 micro-op types

def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitV, A57UnitV,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 6;
  let NumMicroOps = 11;
}

//===----------------------------------------------------------------------===//
// Define Generic 12 micro-op types

def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS,
                                         A57UnitS, A57UnitS, A57UnitS, A57UnitS,
                                         A57UnitV, A57UnitV,
                                         A57UnitV, A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 12;
}

//===----------------------------------------------------------------------===//
// Define Generic 13 micro-op types

def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI,
                                            A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS, A57UnitS,
                                            A57UnitS, A57UnitS,
                                            A57UnitV, A57UnitV,
                                            A57UnitV, A57UnitV]> {
  let Latency     = 8;
  let NumMicroOps = 13;
}

003 File Manager

Editing: AArch64SchedA57WriteRes.td

Upload File

Create Folder