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📄 AMDGPU.h(11.46 KB)
📄 AMDGPU.td(36.97 KB)
📄 AMDGPUAliasAnalysis.cpp(5.58 KB)
📄 AMDGPUAliasAnalysis.h(3.32 KB)
📄 AMDGPUAlwaysInlinePass.cpp(4.83 KB)
📄 AMDGPUAnnotateKernelFeatures.cpp(11.94 KB)
📄 AMDGPUAnnotateUniformValues.cpp(6.13 KB)
📄 AMDGPUArgumentUsageInfo.cpp(7.66 KB)
📄 AMDGPUArgumentUsageInfo.h(4.81 KB)
📄 AMDGPUAsmPrinter.cpp(50.42 KB)
📄 AMDGPUAsmPrinter.h(5.13 KB)
📄 AMDGPUAtomicOptimizer.cpp(23.79 KB)
📄 AMDGPUCallLowering.cpp(28.66 KB)
📄 AMDGPUCallLowering.h(2.37 KB)
📄 AMDGPUCallingConv.td(7.33 KB)
📄 AMDGPUCodeGenPrepare.cpp(46.42 KB)
📄 AMDGPUCombine.td(2.79 KB)
📄 AMDGPUExportClustering.cpp(4.52 KB)
📄 AMDGPUExportClustering.h(533 B)
📄 AMDGPUFeatures.td(1.81 KB)
📄 AMDGPUFixFunctionBitcasts.cpp(1.87 KB)
📄 AMDGPUFrameLowering.cpp(1.98 KB)
📄 AMDGPUFrameLowering.h(1.39 KB)
📄 AMDGPUGISel.td(11.57 KB)
📄 AMDGPUGenRegisterBankInfo.def(5.83 KB)
📄 AMDGPUGlobalISelUtils.cpp(1.77 KB)
📄 AMDGPUGlobalISelUtils.h(2.07 KB)
📄 AMDGPUHSAMetadataStreamer.cpp(31.21 KB)
📄 AMDGPUHSAMetadataStreamer.h(5.46 KB)
📄 AMDGPUISelDAGToDAG.cpp(101.59 KB)
📄 AMDGPUISelLowering.cpp(168.65 KB)
📄 AMDGPUISelLowering.h(19.23 KB)
📄 AMDGPUInline.cpp(7.97 KB)
📄 AMDGPUInstrInfo.cpp(1.71 KB)
📄 AMDGPUInstrInfo.h(1.66 KB)
📄 AMDGPUInstrInfo.td(17.18 KB)
📄 AMDGPUInstructionSelector.cpp(128.53 KB)
📄 AMDGPUInstructionSelector.h(11.04 KB)
📄 AMDGPUInstructions.td(25.36 KB)
📄 AMDGPULegalizerInfo.cpp(149.32 KB)
📄 AMDGPULegalizerInfo.h(8.49 KB)
📄 AMDGPULibCalls.cpp(53.89 KB)
📄 AMDGPULibFunc.cpp(37.85 KB)
📄 AMDGPULibFunc.h(10.99 KB)
📄 AMDGPULowerIntrinsics.cpp(4.55 KB)
📄 AMDGPULowerKernelArguments.cpp(8.89 KB)
📄 AMDGPULowerKernelAttributes.cpp(7.78 KB)
📄 AMDGPUMCInstLower.cpp(14.27 KB)
📄 AMDGPUMachineCFGStructurizer.cpp(101.97 KB)
📄 AMDGPUMachineFunction.cpp(2.24 KB)
📄 AMDGPUMachineFunction.h(2.13 KB)
📄 AMDGPUMachineModuleInfo.cpp(1.34 KB)
📄 AMDGPUMachineModuleInfo.h(5.46 KB)
📄 AMDGPUMacroFusion.cpp(2.28 KB)
📄 AMDGPUMacroFusion.h(679 B)
📄 AMDGPUOpenCLEnqueuedBlockLowering.cpp(5.31 KB)
📄 AMDGPUPTNote.h(1.29 KB)
📄 AMDGPUPerfHintAnalysis.cpp(12.17 KB)
📄 AMDGPUPerfHintAnalysis.h(1.67 KB)
📄 AMDGPUPostLegalizerCombiner.cpp(12.02 KB)
📄 AMDGPUPreLegalizerCombiner.cpp(5.45 KB)
📄 AMDGPUPrintfRuntimeBinding.cpp(21.7 KB)
📄 AMDGPUPromoteAlloca.cpp(35.24 KB)
📄 AMDGPUPropagateAttributes.cpp(11.76 KB)
📄 AMDGPURegBankCombiner.cpp(5.36 KB)
📄 AMDGPURegisterBankInfo.cpp(161.67 KB)
📄 AMDGPURegisterBankInfo.h(7.41 KB)
📄 AMDGPURegisterBanks.td(921 B)
📄 AMDGPURewriteOutArguments.cpp(15.82 KB)
📄 AMDGPUSearchableTables.td(21.04 KB)
📄 AMDGPUSubtarget.cpp(29.62 KB)
📄 AMDGPUSubtarget.h(35.82 KB)
📄 AMDGPUTargetMachine.cpp(42.67 KB)
📄 AMDGPUTargetMachine.h(4.52 KB)
📄 AMDGPUTargetObjectFile.cpp(1.54 KB)
📄 AMDGPUTargetObjectFile.h(1.14 KB)
📄 AMDGPUTargetTransformInfo.cpp(39.07 KB)
📄 AMDGPUTargetTransformInfo.h(11.11 KB)
📄 AMDGPUUnifyDivergentExitNodes.cpp(13.84 KB)
📄 AMDGPUUnifyMetadata.cpp(4.46 KB)
📄 AMDILCFGStructurizer.cpp(56.32 KB)
📄 AMDKernelCodeT.h(32.84 KB)
📁 AsmParser
📄 BUFInstructions.td(110.75 KB)
📄 CaymanInstructions.td(7.93 KB)
📄 DSInstructions.td(52.37 KB)
📁 Disassembler
📄 EvergreenInstructions.td(28.24 KB)
📄 FLATInstructions.td(66.93 KB)
📄 GCNDPPCombine.cpp(19.92 KB)
📄 GCNHazardRecognizer.cpp(45.3 KB)
📄 GCNHazardRecognizer.h(3.96 KB)
📄 GCNILPSched.cpp(11.3 KB)
📄 GCNIterativeScheduler.cpp(20.62 KB)
📄 GCNIterativeScheduler.h(4.16 KB)
📄 GCNMinRegStrategy.cpp(8.47 KB)
📄 GCNNSAReassign.cpp(10.92 KB)
📄 GCNProcessors.td(4.84 KB)
📄 GCNRegBankReassign.cpp(26.68 KB)
📄 GCNRegPressure.cpp(16.27 KB)
📄 GCNRegPressure.h(9.15 KB)
📄 GCNSchedStrategy.cpp(21.67 KB)
📄 GCNSchedStrategy.h(3.77 KB)
📁 MCTargetDesc
📄 MIMGInstructions.td(39.85 KB)
📄 R600.td(1.51 KB)
📄 R600AsmPrinter.cpp(4.46 KB)
📄 R600AsmPrinter.h(1.5 KB)
📄 R600ClauseMergePass.cpp(7.38 KB)
📄 R600ControlFlowFinalizer.cpp(23.4 KB)
📄 R600Defines.h(4.25 KB)
📄 R600EmitClauseMarkers.cpp(12.1 KB)
📄 R600ExpandSpecialInstrs.cpp(10.11 KB)
📄 R600FrameLowering.cpp(1.83 KB)
📄 R600FrameLowering.h(1.25 KB)
📄 R600ISelLowering.cpp(81.88 KB)
📄 R600ISelLowering.h(4.8 KB)
📄 R600InstrFormats.td(11.58 KB)
📄 R600InstrInfo.cpp(49.47 KB)
📄 R600InstrInfo.h(13.7 KB)
📄 R600Instructions.td(55.13 KB)
📄 R600MachineFunctionInfo.cpp(551 B)
📄 R600MachineFunctionInfo.h(824 B)
📄 R600MachineScheduler.cpp(13.57 KB)
📄 R600MachineScheduler.h(2.53 KB)
📄 R600OpenCLImageTypeLoweringPass.cpp(11.75 KB)
📄 R600OptimizeVectorRegisters.cpp(13.4 KB)
📄 R600Packetizer.cpp(13.4 KB)
📄 R600Processors.td(4.42 KB)
📄 R600RegisterInfo.cpp(3.95 KB)
📄 R600RegisterInfo.h(2 KB)
📄 R600RegisterInfo.td(9.75 KB)
📄 R600Schedule.td(1.62 KB)
📄 R700Instructions.td(783 B)
📄 SIAddIMGInit.cpp(6.24 KB)
📄 SIAnnotateControlFlow.cpp(11.18 KB)
📄 SIDefines.h(20.86 KB)
📄 SIFixSGPRCopies.cpp(29.46 KB)
📄 SIFixVGPRCopies.cpp(2 KB)
📄 SIFixupVectorISel.cpp(8.75 KB)
📄 SIFoldOperands.cpp(54.56 KB)
📄 SIFormMemoryClauses.cpp(12.76 KB)
📄 SIFrameLowering.cpp(48.08 KB)
📄 SIFrameLowering.h(2.98 KB)
📄 SIISelLowering.cpp(423.43 KB)
📄 SIISelLowering.h(22.13 KB)
📄 SIInsertHardClauses.cpp(7.01 KB)
📄 SIInsertSkips.cpp(15.29 KB)
📄 SIInsertWaitcnts.cpp(58.33 KB)
📄 SIInstrFormats.td(9.44 KB)
📄 SIInstrInfo.cpp(247.15 KB)
📄 SIInstrInfo.h(41.24 KB)
📄 SIInstrInfo.td(90.7 KB)
📄 SIInstructions.td(77.7 KB)
📄 SILoadStoreOptimizer.cpp(76.21 KB)
📄 SILowerControlFlow.cpp(22.66 KB)
📄 SILowerI1Copies.cpp(27.83 KB)
📄 SILowerSGPRSpills.cpp(12.68 KB)
📄 SIMachineFunctionInfo.cpp(20.01 KB)
📄 SIMachineFunctionInfo.h(26.91 KB)
📄 SIMachineScheduler.cpp(69.44 KB)
📄 SIMachineScheduler.h(15.65 KB)
📄 SIMemoryLegalizer.cpp(45.84 KB)
📄 SIModeRegister.cpp(17.43 KB)
📄 SIOptimizeExecMasking.cpp(12.81 KB)
📄 SIOptimizeExecMaskingPreRA.cpp(11.13 KB)
📄 SIPeepholeSDWA.cpp(42.84 KB)
📄 SIPostRABundler.cpp(3.6 KB)
📄 SIPreAllocateWWMRegs.cpp(6.09 KB)
📄 SIPreEmitPeephole.cpp(10.51 KB)
📄 SIProgramInfo.h(2.04 KB)
📄 SIRegisterInfo.cpp(71.51 KB)
📄 SIRegisterInfo.h(13.04 KB)
📄 SIRegisterInfo.td(37.28 KB)
📄 SIRemoveShortExecBranches.cpp(4.96 KB)
📄 SISchedule.td(7.58 KB)
📄 SIShrinkInstructions.cpp(26.86 KB)
📄 SIWholeQuadMode.cpp(30.22 KB)
📄 SMInstructions.td(48.14 KB)
📄 SOPInstructions.td(60.51 KB)
📁 TargetInfo
📁 Utils
📄 VIInstrFormats.td(645 B)
📄 VOP1Instructions.td(35.53 KB)
📄 VOP2Instructions.td(65.04 KB)
📄 VOP3Instructions.td(53.14 KB)
📄 VOP3PInstructions.td(26.47 KB)
📄 VOPCInstructions.td(63.31 KB)
📄 VOPInstructions.td(23.76 KB)

Editing: AMDGPUGenRegisterBankInfo.def

//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
/// This file defines all the static objects used by AMDGPURegisterBankInfo.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//

namespace llvm {
namespace AMDGPU {

enum PartialMappingIdx {
  None = - 1,
  PM_SGPR1  = 1,
  PM_SGPR16 = 5,
  PM_SGPR32 = 6,
  PM_SGPR64 = 7,
  PM_SGPR128 = 8,
  PM_SGPR256 = 9,
  PM_SGPR512 = 10,
  PM_SGPR1024 = 11,
  PM_VGPR1  = 12,
  PM_VGPR16 = 16,
  PM_VGPR32 = 17,
  PM_VGPR64 = 18,
  PM_VGPR128 = 19,
  PM_VGPR256 = 20,
  PM_VGPR512 = 21,
  PM_VGPR1024 = 22,
  PM_SGPR96 = 23,
  PM_VGPR96 = 24,
  PM_AGPR96 = 25,
  PM_AGPR32 = 31,
  PM_AGPR64 = 32,
  PM_AGPR128 = 33,
  PM_AGPR512 = 34,
  PM_AGPR1024 = 35
};

const RegisterBankInfo::PartialMapping PartMappings[] {
  // StartIdx, Length, RegBank
  {0, 1,  VCCRegBank},

{0, 1,  SGPRRegBank}, // SGPR begin
  {0, 16, SGPRRegBank},
  {0, 32, SGPRRegBank},
  {0, 64, SGPRRegBank},
  {0, 128, SGPRRegBank},
  {0, 256, SGPRRegBank},
  {0, 512, SGPRRegBank},
  {0, 1024, SGPRRegBank},

{0, 1,  VGPRRegBank}, // VGPR begin
  {0, 16, VGPRRegBank},
  {0, 32, VGPRRegBank},
  {0, 64, VGPRRegBank},
  {0, 128, VGPRRegBank},
  {0, 256, VGPRRegBank},
  {0, 512, VGPRRegBank},
  {0, 1024, VGPRRegBank},
  {0, 96, SGPRRegBank},
  {0, 96, VGPRRegBank},
  {0, 96, AGPRRegBank},

{0, 32, AGPRRegBank}, // AGPR begin
  {0, 64, AGPRRegBank},
  {0, 128, AGPRRegBank},
  {0, 512, AGPRRegBank},
  {0, 1024, AGPRRegBank}
};

const RegisterBankInfo::ValueMapping ValMappings[] {
  // VCC
  {&PartMappings[0], 1},

// SGPRs
  {&PartMappings[1], 1}, // 1
  {nullptr, 0}, // Illegal power of 2 sizes
  {nullptr, 0},
  {nullptr, 0},
  {&PartMappings[2], 1}, // 16
  {&PartMappings[3], 1}, // 32
  {&PartMappings[4], 1}, // 64
  {&PartMappings[5], 1}, // 128
  {&PartMappings[6], 1}, // 256
  {&PartMappings[7], 1}, // 512
  {&PartMappings[8], 1}, // 1024

// VGPRs
  {&PartMappings[9], 1}, // 1
  {nullptr, 0},
  {nullptr, 0},
  {nullptr, 0},
  {&PartMappings[10], 1}, // 16
  {&PartMappings[11], 1}, // 32
  {&PartMappings[12], 1}, // 64
  {&PartMappings[13], 1}, // 128
  {&PartMappings[14], 1}, // 256
  {&PartMappings[15], 1}, // 512
  {&PartMappings[16], 1}, // 1024
  {&PartMappings[17], 1},
  {&PartMappings[18], 1},
  {&PartMappings[19], 1},

// AGPRs
  {nullptr, 0},
  {nullptr, 0},
  {nullptr, 0},
  {nullptr, 0},
  {nullptr, 0},
  {&PartMappings[20], 1}, // 32
  {&PartMappings[21], 1}, // 64
  {&PartMappings[22], 1}, // 128
  {nullptr, 0},
  {&PartMappings[23], 1}, // 512
  {&PartMappings[24], 1}  // 1024
};

const RegisterBankInfo::PartialMapping SGPROnly64BreakDown[] {
  {0, 32, SGPRRegBank}, // 32-bit op
  {0, 32, SGPRRegBank}, // 2x32-bit op
  {32, 32, SGPRRegBank},
  {0, 64, SGPRRegBank}, // <2x32-bit> op

{0, 32, VGPRRegBank}, // 32-bit op
  {0, 32, VGPRRegBank}, // 2x32-bit op
  {32, 32, VGPRRegBank},
};

// For some instructions which can operate 64-bit only for the scalar
// version. Otherwise, these need to be split into 2 32-bit operations.
const RegisterBankInfo::ValueMapping ValMappingsSGPR64OnlyVGPR32[] {
  /*32-bit sgpr*/     {&SGPROnly64BreakDown[0], 1},
  /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
  /*64-bit sgpr */    {&SGPROnly64BreakDown[3], 1},

/*32-bit vgpr*/     {&SGPROnly64BreakDown[4], 1},
  /*2 x 32-bit vgpr*/ {&SGPROnly64BreakDown[5], 2}
};

enum ValueMappingIdx {
  SGPRStartIdx = 1,
  VGPRStartIdx = 12,
  AGPRStartIdx = 26
};

const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
                                                      unsigned Size) {
  unsigned Idx;
  switch (Size) {
  case 1:
    if (BankID == AMDGPU::VCCRegBankID)
      return &ValMappings[0];

Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR1 : PM_VGPR1;
    break;
  case 96:
    switch (BankID) {
      case AMDGPU::VGPRRegBankID:
        Idx = PM_VGPR96;
        break;
      case AMDGPU::SGPRRegBankID:
        Idx = PM_SGPR96;
        break;
      case AMDGPU::AGPRRegBankID:
        Idx = PM_AGPR96;
        break;
      default: llvm_unreachable("Invalid register bank");
    }
    break;
  default:
    switch (BankID) {
      case AMDGPU::VGPRRegBankID:
        Idx = VGPRStartIdx;
        break;
      case AMDGPU::SGPRRegBankID:
        Idx = SGPRStartIdx;
        break;
      case AMDGPU::AGPRRegBankID:
        Idx = AGPRStartIdx;
        break;
      default: llvm_unreachable("Invalid register bank");
    }
    Idx += Log2_32_Ceil(Size);
    break;
  }

assert(Log2_32_Ceil(Size) == Log2_32_Ceil(ValMappings[Idx].BreakDown->Length));
  assert(BankID == ValMappings[Idx].BreakDown->RegBank->getID());

return &ValMappings[Idx];
}

const RegisterBankInfo::ValueMapping *getValueMappingSGPR64Only(unsigned BankID,
                                                                unsigned Size) {
  if (Size != 64)
    return getValueMapping(BankID, Size);

if (BankID == AMDGPU::VGPRRegBankID)
    return &ValMappingsSGPR64OnlyVGPR32[4];

assert(BankID == AMDGPU::SGPRRegBankID);
  return &ValMappingsSGPR64OnlyVGPR32[2];
}

/// Split any 64-bit value into 2 32-bit pieces. Unlike
/// getValueMappingSGPR64Only, this splits both VGPRs and SGPRs.
const RegisterBankInfo::ValueMapping *getValueMappingSplit64(unsigned BankID,
                                                             unsigned Size) {
  assert(Size == 64);
  if (BankID == AMDGPU::VGPRRegBankID)
    return &ValMappingsSGPR64OnlyVGPR32[4];

assert(BankID == AMDGPU::SGPRRegBankID);
  return &ValMappingsSGPR64OnlyVGPR32[1];
}

} // End AMDGPU namespace.
} // End llvm namespace.

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