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📁 ..
📄 A15SDOptimizer.cpp(24.01 KB)
📄 ARM.h(2.78 KB)
📄 ARM.td(73.6 KB)
📄 ARMAsmPrinter.cpp(80.17 KB)
📄 ARMAsmPrinter.h(5.74 KB)
📄 ARMBaseInstrInfo.cpp(209.03 KB)
📄 ARMBaseInstrInfo.h(36.07 KB)
📄 ARMBaseRegisterInfo.cpp(34.2 KB)
📄 ARMBaseRegisterInfo.h(7.84 KB)
📄 ARMBasicBlockInfo.cpp(5.18 KB)
📄 ARMBasicBlockInfo.h(5.25 KB)
📄 ARMCallLowering.cpp(19.74 KB)
📄 ARMCallLowering.h(1.89 KB)
📄 ARMCallingConv.cpp(11.8 KB)
📄 ARMCallingConv.h(2.43 KB)
📄 ARMCallingConv.td(14.63 KB)
📄 ARMConstantIslandPass.cpp(90.84 KB)
📄 ARMConstantPoolValue.cpp(11.53 KB)
📄 ARMConstantPoolValue.h(10.1 KB)
📄 ARMExpandPseudoInsts.cpp(115.56 KB)
📄 ARMFastISel.cpp(106.14 KB)
📄 ARMFeatures.h(2.48 KB)
📄 ARMFrameLowering.cpp(102.32 KB)
📄 ARMFrameLowering.h(4.02 KB)
📄 ARMHazardRecognizer.cpp(3.41 KB)
📄 ARMHazardRecognizer.h(1.54 KB)
📄 ARMISelDAGToDAG.cpp(206.42 KB)
📄 ARMISelLowering.cpp(728.6 KB)
📄 ARMISelLowering.h(38.98 KB)
📄 ARMInstrCDE.td(24.04 KB)
📄 ARMInstrFormats.td(93.92 KB)
📄 ARMInstrInfo.cpp(4.2 KB)
📄 ARMInstrInfo.h(1.49 KB)
📄 ARMInstrInfo.td(243.51 KB)
📄 ARMInstrMVE.td(299.67 KB)
📄 ARMInstrNEON.td(436.25 KB)
📄 ARMInstrThumb.td(65.92 KB)
📄 ARMInstrThumb2.td(211.06 KB)
📄 ARMInstrVFP.td(110.46 KB)
📄 ARMInstructionSelector.cpp(39.12 KB)
📄 ARMLegalizerInfo.cpp(18.8 KB)
📄 ARMLegalizerInfo.h(2.41 KB)
📄 ARMLoadStoreOptimizer.cpp(94.44 KB)
📄 ARMLowOverheadLoops.cpp(60.28 KB)
📄 ARMMCInstLower.cpp(7.2 KB)
📄 ARMMachineFunctionInfo.cpp(821 B)
📄 ARMMachineFunctionInfo.h(9.68 KB)
📄 ARMMacroFusion.cpp(2.36 KB)
📄 ARMMacroFusion.h(966 B)
📄 ARMOptimizeBarriersPass.cpp(3.43 KB)
📄 ARMParallelDSP.cpp(26.82 KB)
📄 ARMPerfectShuffle.h(382.02 KB)
📄 ARMPredicates.td(14.16 KB)
📄 ARMRegisterBankInfo.cpp(18.18 KB)
📄 ARMRegisterBankInfo.h(1.41 KB)
📄 ARMRegisterBanks.td(577 B)
📄 ARMRegisterInfo.cpp(685 B)
📄 ARMRegisterInfo.h(845 B)
📄 ARMRegisterInfo.td(24.53 KB)
📄 ARMSchedule.td(15.13 KB)
📄 ARMScheduleA57.td(62.61 KB)
📄 ARMScheduleA57WriteRes.td(11.43 KB)
📄 ARMScheduleA8.td(49.59 KB)
📄 ARMScheduleA9.td(130.35 KB)
📄 ARMScheduleM4.td(4.77 KB)
📄 ARMScheduleR52.td(44.27 KB)
📄 ARMScheduleSwift.td(50.53 KB)
📄 ARMScheduleV6.td(12.34 KB)
📄 ARMSelectionDAGInfo.cpp(9.21 KB)
📄 ARMSelectionDAGInfo.h(2.81 KB)
📄 ARMSubtarget.cpp(16.73 KB)
📄 ARMSubtarget.h(31.56 KB)
📄 ARMSystemRegister.td(5.42 KB)
📄 ARMTargetMachine.cpp(19.74 KB)
📄 ARMTargetMachine.h(3.48 KB)
📄 ARMTargetObjectFile.cpp(3.75 KB)
📄 ARMTargetObjectFile.h(1.67 KB)
📄 ARMTargetTransformInfo.cpp(63.49 KB)
📄 ARMTargetTransformInfo.h(10.22 KB)
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 MLxExpansionPass.cpp(11.56 KB)
📄 MVEGatherScatterLowering.cpp(40.3 KB)
📄 MVETailPredication.cpp(23.2 KB)
📄 MVEVPTBlockPass.cpp(10.77 KB)
📄 MVEVPTOptimisationsPass.cpp(16.46 KB)
📁 TargetInfo
📄 Thumb1FrameLowering.cpp(39.45 KB)
📄 Thumb1FrameLowering.h(3.48 KB)
📄 Thumb1InstrInfo.cpp(5.73 KB)
📄 Thumb1InstrInfo.h(2.38 KB)
📄 Thumb2ITBlockPass.cpp(9.09 KB)
📄 Thumb2InstrInfo.cpp(26.43 KB)
📄 Thumb2InstrInfo.h(3.75 KB)
📄 Thumb2SizeReduction.cpp(40.25 KB)
📄 ThumbRegisterInfo.cpp(21.75 KB)
📄 ThumbRegisterInfo.h(2.44 KB)
📁 Utils

Editing: ARMSystemRegister.td

//===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

include "llvm/TableGen/SearchableTable.td"

//===----------------------------------------------------------------------===//
//  Declarations that describe the ARM system-registers
//===----------------------------------------------------------------------===//

// M-Class System Registers.
// 'Mask' bits create unique keys for searches.
//
class MClassSysReg<bits<1> UniqMask1,
                   bits<1> UniqMask2,
                   bits<1> UniqMask3,
                   bits<12> Enc12,
                   string name> : SearchableTable {
  let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
  string Name;
  bits<13> M1Encoding12;
  bits<10> M2M3Encoding8;
  bits<12> Encoding;

let Name = name;
  let EnumValueField = "M1Encoding12";
  let EnumValueField = "M2M3Encoding8";
  let EnumValueField = "Encoding";

let M1Encoding12{12}    = UniqMask1;
  let M1Encoding12{11-00} = Enc12;
  let Encoding            = Enc12;

let M2M3Encoding8{9}    = UniqMask2;
  let M2M3Encoding8{8}    = UniqMask3;
  let M2M3Encoding8{7-0}  = Enc12{7-0};
  code Requires           = [{ {} }];
}

// [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr.
//                 Mask1 Mask2 Mask3 Enc12, Name
let Requires = [{ {ARM::FeatureDSP} }] in {
def : MClassSysReg<0,    0,    0,    0x400, "apsr_g">;
def : MClassSysReg<0,    1,    1,    0xc00, "apsr_nzcvqg">;
def : MClassSysReg<0,    0,    0,    0x401, "iapsr_g">;
def : MClassSysReg<0,    1,    1,    0xc01, "iapsr_nzcvqg">;
def : MClassSysReg<0,    0,    0,    0x402, "eapsr_g">;
def : MClassSysReg<0,    1,    1,    0xc02, "eapsr_nzcvqg">;
def : MClassSysReg<0,    0,    0,    0x403, "xpsr_g">;
def : MClassSysReg<0,    1,    1,    0xc03, "xpsr_nzcvqg">;
}

def : MClassSysReg<0,    0,    1,    0x800, "apsr">;
def : MClassSysReg<1,    1,    0,    0x800, "apsr_nzcvq">;
def : MClassSysReg<0,    0,    1,    0x801, "iapsr">;
def : MClassSysReg<1,    1,    0,    0x801, "iapsr_nzcvq">;
def : MClassSysReg<0,    0,    1,    0x802, "eapsr">;
def : MClassSysReg<1,    1,    0,    0x802, "eapsr_nzcvq">;
def : MClassSysReg<0,    0,    1,    0x803, "xpsr">;
def : MClassSysReg<1,    1,    0,    0x803, "xpsr_nzcvq">;

def : MClassSysReg<0,    0,    1,    0x805, "ipsr">;
def : MClassSysReg<0,    0,    1,    0x806, "epsr">;
def : MClassSysReg<0,    0,    1,    0x807, "iepsr">;
def : MClassSysReg<0,    0,    1,    0x808, "msp">;
def : MClassSysReg<0,    0,    1,    0x809, "psp">;

let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
def : MClassSysReg<0,    0,    1,    0x80a, "msplim">;
def : MClassSysReg<0,    0,    1,    0x80b, "psplim">;
}

def : MClassSysReg<0,    0,    1,    0x810, "primask">;

def : MClassSysReg<0,    0,    1,    0x814, "control">;

let Requires = [{ {ARM::Feature8MSecExt} }] in {
def : MClassSysReg<0,    0,    1,    0x888, "msp_ns">;
def : MClassSysReg<0,    0,    1,    0x889, "psp_ns">;
}

let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
def : MClassSysReg<0,    0,    1,    0x88a, "msplim_ns">;
def : MClassSysReg<0,    0,    1,    0x88b, "psplim_ns">;
}

def : MClassSysReg<0,    0,    1,    0x890, "primask_ns">;

let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
def : MClassSysReg<0,    0,    1,    0x891, "basepri_ns">;
def : MClassSysReg<0,    0,    1,    0x893, "faultmask_ns">;
}

let Requires = [{ {ARM::Feature8MSecExt} }] in {
def : MClassSysReg<0,    0,    1,    0x894, "control_ns">;
def : MClassSysReg<0,    0,    1,    0x898, "sp_ns">;
}

// Banked Registers
//
class BankedReg<string name,  bits<8> enc>
               : SearchableTable {
  string Name;
  bits<8> Encoding;
  let Name = name;
  let Encoding = enc;
  let SearchableFields = ["Name", "Encoding"];
}

// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
// and bit 5 is R.
def : BankedReg<"r8_usr",   0x00>;
def : BankedReg<"r9_usr",   0x01>;
def : BankedReg<"r10_usr",  0x02>;
def : BankedReg<"r11_usr",  0x03>;
def : BankedReg<"r12_usr",  0x04>;
def : BankedReg<"sp_usr",   0x05>;
def : BankedReg<"lr_usr",   0x06>;
def : BankedReg<"r8_fiq",   0x08>;
def : BankedReg<"r9_fiq",   0x09>;
def : BankedReg<"r10_fiq",  0x0a>;
def : BankedReg<"r11_fiq",  0x0b>;
def : BankedReg<"r12_fiq",  0x0c>;
def : BankedReg<"sp_fiq",   0x0d>;
def : BankedReg<"lr_fiq",   0x0e>;
def : BankedReg<"lr_irq",   0x10>;
def : BankedReg<"sp_irq",   0x11>;
def : BankedReg<"lr_svc",   0x12>;
def : BankedReg<"sp_svc",   0x13>;
def : BankedReg<"lr_abt",   0x14>;
def : BankedReg<"sp_abt",   0x15>;
def : BankedReg<"lr_und",   0x16>;
def : BankedReg<"sp_und",   0x17>;
def : BankedReg<"lr_mon",   0x1c>;
def : BankedReg<"sp_mon",   0x1d>;
def : BankedReg<"elr_hyp",  0x1e>;
def : BankedReg<"sp_hyp",   0x1f>;
def : BankedReg<"spsr_fiq", 0x2e>;
def : BankedReg<"spsr_irq", 0x30>;
def : BankedReg<"spsr_svc", 0x32>;
def : BankedReg<"spsr_abt", 0x34>;
def : BankedReg<"spsr_und", 0x36>;
def : BankedReg<"spsr_mon", 0x3c>;
def : BankedReg<"spsr_hyp", 0x3e>;

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Editing: ARMSystemRegister.td

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