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AccelTable.h
(13.54 KB)
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Analysis.h
(6.04 KB)
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AntiDepBreaker.h
(3.78 KB)
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AsmPrinter.h
(27.35 KB)
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AsmPrinterHandler.h
(2.6 KB)
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AtomicExpandUtils.h
(2.49 KB)
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BasicTTIImpl.h
(73.64 KB)
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BuiltinGCs.h
(1008 B)
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CSEConfigBase.h
(1.09 KB)
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CalcSpillWeights.h
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CallingConvLower.h
(21 KB)
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CommandFlags.h
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CostTable.h
(1.87 KB)
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DAGCombine.h
(606 B)
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DFAPacketizer.h
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DIE.h
(32.19 KB)
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DIEValue.def
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DbgEntityHistoryCalculator.h
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DebugHandlerBase.h
(4.68 KB)
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DwarfStringPoolEntry.h
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EdgeBundles.h
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ExecutionDomainFix.h
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ExpandReductions.h
(726 B)
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FastISel.h
(22.87 KB)
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FaultMaps.h
(6.66 KB)
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FunctionLoweringInfo.h
(9.68 KB)
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GCMetadata.h
(7.24 KB)
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GCMetadataPrinter.h
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GCStrategy.h
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GlobalISel
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ISDOpcodes.h
(52.75 KB)
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IndirectThunks.h
(3.85 KB)
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IntrinsicLowering.h
(1.67 KB)
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LatencyPriorityQueue.h
(3.09 KB)
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LazyMachineBlockFrequencyInfo.h
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LexicalScopes.h
(10.06 KB)
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LinkAllAsmWriterComponents.h
(1.34 KB)
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LinkAllCodegenComponents.h
(2.18 KB)
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LiveInterval.h
(37.24 KB)
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LiveIntervalCalc.h
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LiveIntervalUnion.h
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LiveIntervals.h
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LivePhysRegs.h
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LiveRangeCalc.h
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LiveRangeEdit.h
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LiveRegMatrix.h
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LiveRegUnits.h
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LiveStacks.h
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LiveVariables.h
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LoopTraversal.h
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LowLevelType.h
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MBFIWrapper.h
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MIRFormatter.h
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MIRParser
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MIRPrinter.h
(1.73 KB)
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MIRYamlMapping.h
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MachORelocation.h
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MachineBasicBlock.h
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MachineBlockFrequencyInfo.h
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MachineBranchProbabilityInfo.h
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MachineCombinerPattern.h
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MachineConstantPool.h
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MachineDominanceFrontier.h
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MachineDominators.h
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MachineFrameInfo.h
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MachineFunction.h
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MachineFunctionPass.h
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MachineInstr.h
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MachineInstrBuilder.h
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MachineInstrBundle.h
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MachineInstrBundleIterator.h
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MachineJumpTableInfo.h
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MachineLoopInfo.h
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MachineLoopUtils.h
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MachineMemOperand.h
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MachineModuleInfo.h
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MachineModuleInfoImpls.h
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MachineOperand.h
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MachineOptimizationRemarkEmitter.h
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MachineOutliner.h
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MachinePassRegistry.h
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MachinePipeliner.h
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MachinePostDominators.h
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MachineRegionInfo.h
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MachineRegisterInfo.h
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MachineSSAUpdater.h
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MachineScheduler.h
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MachineSizeOpts.h
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MachineTraceMetrics.h
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MacroFusion.h
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ModuloSchedule.h
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NonRelocatableStringpool.h
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PBQP
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PBQPRAConstraint.h
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ParallelCG.h
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Passes.h
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PreISelIntrinsicLowering.h
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PseudoSourceValue.h
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RDFGraph.h
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RDFLiveness.h
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RDFRegisters.h
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ReachingDefAnalysis.h
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RegAllocPBQP.h
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RegAllocRegistry.h
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Register.h
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RegisterClassInfo.h
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RegisterPressure.h
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RegisterScavenging.h
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RegisterUsageInfo.h
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ResourcePriorityQueue.h
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RuntimeLibcalls.h
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SDNodeProperties.td
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ScheduleDAG.h
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ScheduleDAGInstrs.h
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ScheduleDAGMutation.h
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ScheduleDFS.h
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ScheduleHazardRecognizer.h
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SchedulerRegistry.h
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ScoreboardHazardRecognizer.h
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SelectionDAG.h
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SelectionDAGAddressAnalysis.h
(3.58 KB)
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SelectionDAGISel.h
(13.48 KB)
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SelectionDAGNodes.h
(91.77 KB)
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SelectionDAGTargetInfo.h
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SlotIndexes.h
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Spiller.h
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StackMaps.h
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StackProtector.h
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SwiftErrorValueTracking.h
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SwitchLoweringUtils.h
(9.51 KB)
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TailDuplicator.h
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TargetCallingConv.h
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TargetFrameLowering.h
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TargetInstrInfo.h
(84.48 KB)
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TargetLowering.h
(194.17 KB)
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TargetLoweringObjectFileImpl.h
(11.63 KB)
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TargetOpcodes.h
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TargetPassConfig.h
(17.9 KB)
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TargetRegisterInfo.h
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TargetSchedule.h
(7.75 KB)
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TargetSubtargetInfo.h
(12.53 KB)
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UnreachableBlockElim.h
(1.39 KB)
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ValueTypes.h
(17.2 KB)
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ValueTypes.td
(11.42 KB)
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VirtRegMap.h
(6.37 KB)
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WasmEHFuncInfo.h
(1.92 KB)
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WinEHFuncInfo.h
(4.01 KB)
Editing: Analysis.h
//===- CodeGen/Analysis.h - CodeGen LLVM IR Analysis Utilities --*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file declares several CodeGen-specific LLVM IR analysis utilities. // //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_ANALYSIS_H #define LLVM_CODEGEN_ANALYSIS_H #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Triple.h" #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/IR/InlineAsm.h" #include "llvm/IR/Instructions.h" #include "llvm/Support/CodeGen.h" namespace llvm { class GlobalValue; class LLT; class MachineBasicBlock; class MachineFunction; class TargetLoweringBase; class TargetLowering; class TargetMachine; struct EVT; /// Compute the linearized index of a member in a nested /// aggregate/struct/array. /// /// Given an LLVM IR aggregate type and a sequence of insertvalue or /// extractvalue indices that identify a member, return the linearized index of /// the start of the member, i.e the number of element in memory before the /// sought one. This is disconnected from the number of bytes. /// /// \param Ty is the type indexed by \p Indices. /// \param Indices is an optional pointer in the indices list to the current /// index. /// \param IndicesEnd is the end of the indices list. /// \param CurIndex is the current index in the recursion. /// /// \returns \p CurIndex plus the linear index in \p Ty the indices list. unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex = 0); inline unsigned ComputeLinearIndex(Type *Ty, ArrayRef<unsigned> Indices, unsigned CurIndex = 0) { return ComputeLinearIndex(Ty, Indices.begin(), Indices.end(), CurIndex); } /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of /// EVTs that represent all the individual underlying /// non-aggregate types that comprise it. /// /// If Offsets is non-null, it points to a vector to be filled in /// with the in-memory offsets of each of the individual values. /// void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl<EVT> &ValueVTs, SmallVectorImpl<uint64_t> *Offsets = nullptr, uint64_t StartingOffset = 0); /// Variant of ComputeValueVTs that also produces the memory VTs. void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl<EVT> &ValueVTs, SmallVectorImpl<EVT> *MemVTs, SmallVectorImpl<uint64_t> *Offsets = nullptr, uint64_t StartingOffset = 0); /// computeValueLLTs - Given an LLVM IR type, compute a sequence of /// LLTs that represent all the individual underlying /// non-aggregate types that comprise it. /// /// If Offsets is non-null, it points to a vector to be filled in /// with the in-memory offsets of each of the individual values. /// void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl<LLT> &ValueTys, SmallVectorImpl<uint64_t> *Offsets = nullptr, uint64_t StartingOffset = 0); /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V. GlobalValue *ExtractTypeInfo(Value *V); /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being /// processed uses a memory 'm' constraint. bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos, const TargetLowering &TLI); /// getFCmpCondCode - Return the ISD condition code corresponding to /// the given LLVM IR floating-point condition code. This includes /// consideration of global floating-point math flags. /// ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred); /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, /// return the equivalent code if we're allowed to assume that NaNs won't occur. ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC); /// getICmpCondCode - Return the ISD condition code corresponding to /// the given LLVM IR integer condition code. /// ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred); /// Test if the given instruction is in a position to be optimized /// with a tail-call. This roughly means that it's in a block with /// a return and there's nothing that needs to be scheduled /// between it and the return. /// /// This function only tests target-independent requirements. bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM); /// Test if given that the input instruction is in the tail call position, if /// there is an attribute mismatch between the caller and the callee that will /// inhibit tail call optimizations. /// \p AllowDifferingSizes is an output parameter which, if forming a tail call /// is permitted, determines whether it's permitted only if the size of the /// caller's and callee's return types match exactly. bool attributesPermitTailCall(const Function *F, const Instruction *I, const ReturnInst *Ret, const TargetLoweringBase &TLI, bool *AllowDifferingSizes = nullptr); /// Test if given that the input instruction is in the tail call position if the /// return type or any attributes of the function will inhibit tail call /// optimization. bool returnTypeIsEligibleForTailCall(const Function *F, const Instruction *I, const ReturnInst *Ret, const TargetLoweringBase &TLI); DenseMap<const MachineBasicBlock *, int> getEHScopeMembership(const MachineFunction &MF); } // End llvm namespace #endif
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