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Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/Hexagon

usr / src / contrib / llvm-project / llvm / lib / Target / Hexagon /

📁 ..
📁 AsmParser
📄 BitTracker.cpp(35.36 KB)
📄 BitTracker.h(17.25 KB)
📁 Disassembler
📄 Hexagon.h(1004 B)
📄 Hexagon.td(17.33 KB)
📄 HexagonArch.h(1.2 KB)
📄 HexagonAsmPrinter.cpp(26.65 KB)
📄 HexagonAsmPrinter.h(2.03 KB)
📄 HexagonBitSimplify.cpp(107.45 KB)
📄 HexagonBitTracker.cpp(39.88 KB)
📄 HexagonBitTracker.h(2.5 KB)
📄 HexagonBlockRanges.cpp(15.85 KB)
📄 HexagonBlockRanges.h(6.97 KB)
📄 HexagonBranchRelaxation.cpp(7.78 KB)
📄 HexagonCFGOptimizer.cpp(8.4 KB)
📄 HexagonCallingConv.td(4.46 KB)
📄 HexagonCommonGEP.cpp(41.47 KB)
📄 HexagonConstExtenders.cpp(70.64 KB)
📄 HexagonConstPropagation.cpp(97.75 KB)
📄 HexagonCopyToCombine.cpp(32.2 KB)
📄 HexagonDepArch.h(2.04 KB)
📄 HexagonDepArch.td(1.87 KB)
📄 HexagonDepDecoders.inc(2.55 KB)
📄 HexagonDepIICHVX.td(113.05 KB)
📄 HexagonDepIICScalar.td(224.12 KB)
📄 HexagonDepITypes.h(1.51 KB)
📄 HexagonDepITypes.td(1.91 KB)
📄 HexagonDepInstrFormats.td(91.89 KB)
📄 HexagonDepInstrInfo.td(1021.44 KB)
📄 HexagonDepMapAsm2Intrin.td(255.17 KB)
📄 HexagonDepMappings.td(64.27 KB)
📄 HexagonDepMask.h(51.94 KB)
📄 HexagonDepOperands.td(12.12 KB)
📄 HexagonDepTimingClasses.h(4.69 KB)
📄 HexagonEarlyIfConv.cpp(37.36 KB)
📄 HexagonExpandCondsets.cpp(48.55 KB)
📄 HexagonFixupHwLoops.cpp(6.54 KB)
📄 HexagonFrameLowering.cpp(97.16 KB)
📄 HexagonFrameLowering.h(7.85 KB)
📄 HexagonGenExtract.cpp(8.61 KB)
📄 HexagonGenInsert.cpp(53.24 KB)
📄 HexagonGenMux.cpp(12.71 KB)
📄 HexagonGenPredicate.cpp(16.25 KB)
📄 HexagonHardwareLoops.cpp(70.32 KB)
📄 HexagonHazardRecognizer.cpp(5.85 KB)
📄 HexagonHazardRecognizer.h(3.58 KB)
📄 HexagonIICHVX.td(1.21 KB)
📄 HexagonIICScalar.td(1.34 KB)
📄 HexagonISelDAGToDAG.cpp(78.63 KB)
📄 HexagonISelDAGToDAG.h(5.88 KB)
📄 HexagonISelDAGToDAGHVX.cpp(68.26 KB)
📄 HexagonISelLowering.cpp(134.65 KB)
📄 HexagonISelLowering.h(22.5 KB)
📄 HexagonISelLoweringHVX.cpp(70.57 KB)
📄 HexagonInstrFormats.td(12.04 KB)
📄 HexagonInstrFormatsV60.td(1.03 KB)
📄 HexagonInstrFormatsV65.td(1.54 KB)
📄 HexagonInstrInfo.cpp(161.08 KB)
📄 HexagonInstrInfo.h(25.31 KB)
📄 HexagonIntrinsics.td(19.21 KB)
📄 HexagonIntrinsicsV5.td(16.8 KB)
📄 HexagonIntrinsicsV60.td(28.9 KB)
📄 HexagonLoopIdiomRecognition.cpp(79.16 KB)
📄 HexagonMCInstLower.cpp(6.25 KB)
📄 HexagonMachineFunctionInfo.cpp(507 B)
📄 HexagonMachineFunctionInfo.h(3.32 KB)
📄 HexagonMachineScheduler.cpp(34.25 KB)
📄 HexagonMachineScheduler.h(8.66 KB)
📄 HexagonMapAsm2IntrinV62.gen.td(8.71 KB)
📄 HexagonMapAsm2IntrinV65.gen.td(12.43 KB)
📄 HexagonNewValueJump.cpp(25.57 KB)
📄 HexagonOperands.td(1.62 KB)
📄 HexagonOptAddrMode.cpp(29.37 KB)
📄 HexagonOptimizeSZextends.cpp(4.74 KB)
📄 HexagonPatterns.td(142.35 KB)
📄 HexagonPatternsHVX.td(22.06 KB)
📄 HexagonPatternsV65.td(2.96 KB)
📄 HexagonPeephole.cpp(10.18 KB)
📄 HexagonPseudo.td(21.62 KB)
📄 HexagonRDFOpt.cpp(9.94 KB)
📄 HexagonRegisterInfo.cpp(12.03 KB)
📄 HexagonRegisterInfo.h(2.88 KB)
📄 HexagonRegisterInfo.td(20.42 KB)
📄 HexagonSchedule.td(2.33 KB)
📄 HexagonScheduleV5.td(1.73 KB)
📄 HexagonScheduleV55.td(1.81 KB)
📄 HexagonScheduleV60.td(4.31 KB)
📄 HexagonScheduleV62.td(1.53 KB)
📄 HexagonScheduleV65.td(1.57 KB)
📄 HexagonScheduleV66.td(1.57 KB)
📄 HexagonScheduleV67.td(1.57 KB)
📄 HexagonScheduleV67T.td(2.51 KB)
📄 HexagonSelectionDAGInfo.cpp(2.35 KB)
📄 HexagonSelectionDAGInfo.h(1.24 KB)
📄 HexagonSplitConst32AndConst64.cpp(4.15 KB)
📄 HexagonSplitDouble.cpp(37.86 KB)
📄 HexagonStoreWidening.cpp(20.47 KB)
📄 HexagonSubtarget.cpp(20.97 KB)
📄 HexagonSubtarget.h(10.59 KB)
📄 HexagonTargetMachine.cpp(16 KB)
📄 HexagonTargetMachine.h(1.77 KB)
📄 HexagonTargetObjectFile.cpp(16.8 KB)
📄 HexagonTargetObjectFile.h(2.17 KB)
📄 HexagonTargetStreamer.h(1.2 KB)
📄 HexagonTargetTransformInfo.cpp(13.11 KB)
📄 HexagonTargetTransformInfo.h(6.27 KB)
📄 HexagonVExtract.cpp(6.64 KB)
📄 HexagonVLIWPacketizer.cpp(67.01 KB)
📄 HexagonVLIWPacketizer.h(6.09 KB)
📄 HexagonVectorLoopCarriedReuse.cpp(23.99 KB)
📄 HexagonVectorPrint.cpp(7.06 KB)
📁 MCTargetDesc
📄 RDFCopy.cpp(6.37 KB)
📄 RDFCopy.h(1.69 KB)
📄 RDFDeadCode.cpp(7.5 KB)
📄 RDFDeadCode.h(2.33 KB)
📁 TargetInfo

Editing: HexagonCallingConv.td

//===- HexagonCallingConv.td ----------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

class CCIfArgIsVarArg<CCAction A>
  : CCIf<"State.isVarArg() && "
         "ValNo >= static_cast<HexagonCCState&>(State)"
         ".getNumNamedVarArgParams()", A>;

def CC_HexagonStack: CallingConv<[
  CCIfType<[i32,v2i16,v4i8],
    CCAssignToStack<4,4>>,
  CCIfType<[i64,v2i32,v4i16,v8i8],
    CCAssignToStack<8,8>>
]>;

def CC_Hexagon_Legacy: CallingConv<[
  CCIfType<[i1,i8,i16],
    CCPromoteToType<i32>>,
  CCIfType<[f32],
    CCBitConvertToType<i32>>,
  CCIfType<[f64],
    CCBitConvertToType<i64>>,

CCIfByVal<
    CCPassByVal<8,8>>,
  CCIfArgIsVarArg<
    CCDelegateTo<CC_HexagonStack>>,

// Pass split values in pairs, allocate odd register if necessary.
  CCIfType<[i32],
    CCIfSplit<
      CCCustom<"CC_SkipOdd">>>,

CCIfType<[i32,v2i16,v4i8],
    CCAssignToReg<[R0,R1,R2,R3,R4,R5]>>,
  // Make sure to allocate any skipped 32-bit register, so it does not get
  // allocated to a subsequent 32-bit value.
  CCIfType<[i64,v2i32,v4i16,v8i8],
    CCCustom<"CC_SkipOdd">>,
  CCIfType<[i64,v2i32,v4i16,v8i8],
    CCAssignToReg<[D0,D1,D2]>>,

CCDelegateTo<CC_HexagonStack>
]>;

def CC_Hexagon: CallingConv<[
  CCIfType<[i1,i8,i16],
    CCPromoteToType<i32>>,
  CCIfType<[f32],
    CCBitConvertToType<i32>>,
  CCIfType<[f64],
    CCBitConvertToType<i64>>,

CCIfByVal<
    CCPassByVal<8,1>>,
  CCIfArgIsVarArg<
    CCDelegateTo<CC_HexagonStack>>,

// Pass split values in pairs, allocate odd register if necessary.
  CCIfType<[i32],
    CCIfSplit<
      CCCustom<"CC_SkipOdd">>>,

CCDelegateTo<CC_HexagonStack>
]>;

def RetCC_Hexagon: CallingConv<[
  CCIfType<[i1,i8,i16],
    CCPromoteToType<i32>>,
  CCIfType<[f32],
    CCBitConvertToType<i32>>,
  CCIfType<[f64],
    CCBitConvertToType<i64>>,

// Small structures are returned in a pair of registers, (which is
  // always r1:0). In such case, what is returned are two i32 values
  // without any additional information (in ArgFlags) stating that
  // they are parts of a structure. Because of that there is no way
  // to differentiate that situation from an attempt to return two
  // values, so always assign R0 and R1.
  CCIfSplit<
    CCAssignToReg<[R0,R1]>>,
  CCIfType<[i32,v2i16,v4i8],
    CCAssignToReg<[R0,R1]>>,
  CCIfType<[i64,v2i32,v4i16,v8i8],
    CCAssignToReg<[D0]>>
]>;

class CCIfHvx64<CCAction A>
  : CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()"
         ".useHVX64BOps()", A>;

class CCIfHvx128<CCAction A>
  : CCIf<"State.getMachineFunction().getSubtarget<HexagonSubtarget>()"
         ".useHVX128BOps()", A>;

def CC_Hexagon_HVX: CallingConv<[
  // HVX 64-byte mode
  CCIfHvx64<
    CCIfType<[v16i32,v32i16,v64i8],
      CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
  CCIfHvx64<
    CCIfType<[v32i32,v64i16,v128i8],
      CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
  CCIfHvx64<
    CCIfType<[v16i32,v32i16,v64i8],
      CCAssignToStack<64,64>>>,
  CCIfHvx64<
    CCIfType<[v32i32,v64i16,v128i8],
      CCAssignToStack<128,64>>>,

// HVX 128-byte mode
  CCIfHvx128<
    CCIfType<[v32i32,v64i16,v128i8],
      CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
  CCIfHvx128<
    CCIfType<[v64i32,v128i16,v256i8],
      CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
  CCIfHvx128<
    CCIfType<[v32i32,v64i16,v128i8],
      CCAssignToStack<128,128>>>,
  CCIfHvx128<
    CCIfType<[v64i32,v128i16,v256i8],
      CCAssignToStack<256,128>>>,

CCDelegateTo<CC_Hexagon>
]>;

def RetCC_Hexagon_HVX: CallingConv<[
  // HVX 64-byte mode
  CCIfHvx64<
    CCIfType<[v16i32,v32i16,v64i8],
      CCAssignToReg<[V0]>>>,
  CCIfHvx64<
    CCIfType<[v32i32,v64i16,v128i8],
      CCAssignToReg<[W0]>>>,

// HVX 128-byte mode
  CCIfHvx128<
    CCIfType<[v32i32,v64i16,v128i8],
      CCAssignToReg<[V0]>>>,
  CCIfHvx128<
    CCIfType<[v64i32,v128i16,v256i8],
      CCAssignToReg<[W0]>>>,

CCDelegateTo<RetCC_Hexagon>
]>;

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Editing: HexagonCallingConv.td

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