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📁 ..
📁 AsmParser
📄 BitTracker.cpp(35.36 KB)
📄 BitTracker.h(17.25 KB)
📁 Disassembler
📄 Hexagon.h(1004 B)
📄 Hexagon.td(17.33 KB)
📄 HexagonArch.h(1.2 KB)
📄 HexagonAsmPrinter.cpp(26.65 KB)
📄 HexagonAsmPrinter.h(2.03 KB)
📄 HexagonBitSimplify.cpp(107.45 KB)
📄 HexagonBitTracker.cpp(39.88 KB)
📄 HexagonBitTracker.h(2.5 KB)
📄 HexagonBlockRanges.cpp(15.85 KB)
📄 HexagonBlockRanges.h(6.97 KB)
📄 HexagonBranchRelaxation.cpp(7.78 KB)
📄 HexagonCFGOptimizer.cpp(8.4 KB)
📄 HexagonCallingConv.td(4.46 KB)
📄 HexagonCommonGEP.cpp(41.47 KB)
📄 HexagonConstExtenders.cpp(70.64 KB)
📄 HexagonConstPropagation.cpp(97.75 KB)
📄 HexagonCopyToCombine.cpp(32.2 KB)
📄 HexagonDepArch.h(2.04 KB)
📄 HexagonDepArch.td(1.87 KB)
📄 HexagonDepDecoders.inc(2.55 KB)
📄 HexagonDepIICHVX.td(113.05 KB)
📄 HexagonDepIICScalar.td(224.12 KB)
📄 HexagonDepITypes.h(1.51 KB)
📄 HexagonDepITypes.td(1.91 KB)
📄 HexagonDepInstrFormats.td(91.89 KB)
📄 HexagonDepInstrInfo.td(1021.44 KB)
📄 HexagonDepMapAsm2Intrin.td(255.17 KB)
📄 HexagonDepMappings.td(64.27 KB)
📄 HexagonDepMask.h(51.94 KB)
📄 HexagonDepOperands.td(12.12 KB)
📄 HexagonDepTimingClasses.h(4.69 KB)
📄 HexagonEarlyIfConv.cpp(37.36 KB)
📄 HexagonExpandCondsets.cpp(48.55 KB)
📄 HexagonFixupHwLoops.cpp(6.54 KB)
📄 HexagonFrameLowering.cpp(97.16 KB)
📄 HexagonFrameLowering.h(7.85 KB)
📄 HexagonGenExtract.cpp(8.61 KB)
📄 HexagonGenInsert.cpp(53.24 KB)
📄 HexagonGenMux.cpp(12.71 KB)
📄 HexagonGenPredicate.cpp(16.25 KB)
📄 HexagonHardwareLoops.cpp(70.32 KB)
📄 HexagonHazardRecognizer.cpp(5.85 KB)
📄 HexagonHazardRecognizer.h(3.58 KB)
📄 HexagonIICHVX.td(1.21 KB)
📄 HexagonIICScalar.td(1.34 KB)
📄 HexagonISelDAGToDAG.cpp(78.63 KB)
📄 HexagonISelDAGToDAG.h(5.88 KB)
📄 HexagonISelDAGToDAGHVX.cpp(68.26 KB)
📄 HexagonISelLowering.cpp(134.65 KB)
📄 HexagonISelLowering.h(22.5 KB)
📄 HexagonISelLoweringHVX.cpp(70.57 KB)
📄 HexagonInstrFormats.td(12.04 KB)
📄 HexagonInstrFormatsV60.td(1.03 KB)
📄 HexagonInstrFormatsV65.td(1.54 KB)
📄 HexagonInstrInfo.cpp(161.08 KB)
📄 HexagonInstrInfo.h(25.31 KB)
📄 HexagonIntrinsics.td(19.21 KB)
📄 HexagonIntrinsicsV5.td(16.8 KB)
📄 HexagonIntrinsicsV60.td(28.9 KB)
📄 HexagonLoopIdiomRecognition.cpp(79.16 KB)
📄 HexagonMCInstLower.cpp(6.25 KB)
📄 HexagonMachineFunctionInfo.cpp(507 B)
📄 HexagonMachineFunctionInfo.h(3.32 KB)
📄 HexagonMachineScheduler.cpp(34.25 KB)
📄 HexagonMachineScheduler.h(8.66 KB)
📄 HexagonMapAsm2IntrinV62.gen.td(8.71 KB)
📄 HexagonMapAsm2IntrinV65.gen.td(12.43 KB)
📄 HexagonNewValueJump.cpp(25.57 KB)
📄 HexagonOperands.td(1.62 KB)
📄 HexagonOptAddrMode.cpp(29.37 KB)
📄 HexagonOptimizeSZextends.cpp(4.74 KB)
📄 HexagonPatterns.td(142.35 KB)
📄 HexagonPatternsHVX.td(22.06 KB)
📄 HexagonPatternsV65.td(2.96 KB)
📄 HexagonPeephole.cpp(10.18 KB)
📄 HexagonPseudo.td(21.62 KB)
📄 HexagonRDFOpt.cpp(9.94 KB)
📄 HexagonRegisterInfo.cpp(12.03 KB)
📄 HexagonRegisterInfo.h(2.88 KB)
📄 HexagonRegisterInfo.td(20.42 KB)
📄 HexagonSchedule.td(2.33 KB)
📄 HexagonScheduleV5.td(1.73 KB)
📄 HexagonScheduleV55.td(1.81 KB)
📄 HexagonScheduleV60.td(4.31 KB)
📄 HexagonScheduleV62.td(1.53 KB)
📄 HexagonScheduleV65.td(1.57 KB)
📄 HexagonScheduleV66.td(1.57 KB)
📄 HexagonScheduleV67.td(1.57 KB)
📄 HexagonScheduleV67T.td(2.51 KB)
📄 HexagonSelectionDAGInfo.cpp(2.35 KB)
📄 HexagonSelectionDAGInfo.h(1.24 KB)
📄 HexagonSplitConst32AndConst64.cpp(4.15 KB)
📄 HexagonSplitDouble.cpp(37.86 KB)
📄 HexagonStoreWidening.cpp(20.47 KB)
📄 HexagonSubtarget.cpp(20.97 KB)
📄 HexagonSubtarget.h(10.59 KB)
📄 HexagonTargetMachine.cpp(16 KB)
📄 HexagonTargetMachine.h(1.77 KB)
📄 HexagonTargetObjectFile.cpp(16.8 KB)
📄 HexagonTargetObjectFile.h(2.17 KB)
📄 HexagonTargetStreamer.h(1.2 KB)
📄 HexagonTargetTransformInfo.cpp(13.11 KB)
📄 HexagonTargetTransformInfo.h(6.27 KB)
📄 HexagonVExtract.cpp(6.64 KB)
📄 HexagonVLIWPacketizer.cpp(67.01 KB)
📄 HexagonVLIWPacketizer.h(6.09 KB)
📄 HexagonVectorLoopCarriedReuse.cpp(23.99 KB)
📄 HexagonVectorPrint.cpp(7.06 KB)
📁 MCTargetDesc
📄 RDFCopy.cpp(6.37 KB)
📄 RDFCopy.h(1.69 KB)
📄 RDFDeadCode.cpp(7.5 KB)
📄 RDFDeadCode.h(2.33 KB)
📁 TargetInfo

Editing: HexagonFixupHwLoops.cpp

//===---- HexagonFixupHwLoops.cpp - Fixup HW loops too far from LOOPn. ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// The loop start address in the LOOPn instruction is encoded as a distance
// from the LOOPn instruction itself. If the start address is too far from
// the LOOPn instruction, the instruction needs to use a constant extender.
// This pass will identify and convert such LOOPn instructions to a proper
// form.
//===----------------------------------------------------------------------===//

#include "Hexagon.h"
#include "HexagonTargetMachine.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Pass.h"

using namespace llvm;

static cl::opt<unsigned> MaxLoopRange(
    "hexagon-loop-range", cl::Hidden, cl::init(200),
    cl::desc("Restrict range of loopN instructions (testing only)"));

namespace llvm {
  FunctionPass *createHexagonFixupHwLoops();
  void initializeHexagonFixupHwLoopsPass(PassRegistry&);
}

namespace {
  struct HexagonFixupHwLoops : public MachineFunctionPass {
  public:
    static char ID;

HexagonFixupHwLoops() : MachineFunctionPass(ID) {
      initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
    }

bool runOnMachineFunction(MachineFunction &MF) override;

MachineFunctionProperties getRequiredProperties() const override {
      return MachineFunctionProperties().set(
          MachineFunctionProperties::Property::NoVRegs);
    }

StringRef getPassName() const override {
      return "Hexagon Hardware Loop Fixup";
    }

void getAnalysisUsage(AnalysisUsage &AU) const override {
      AU.setPreservesCFG();
      MachineFunctionPass::getAnalysisUsage(AU);
    }

private:
    /// Check the offset between each loop instruction and
    /// the loop basic block to determine if we can use the LOOP instruction
    /// or if we need to set the LC/SA registers explicitly.
    bool fixupLoopInstrs(MachineFunction &MF);

/// Replace loop instruction with the constant extended
    /// version if the loop label is too far from the loop instruction.
    void useExtLoopInstr(MachineFunction &MF,
                         MachineBasicBlock::iterator &MII);
  };

char HexagonFixupHwLoops::ID = 0;
}

INITIALIZE_PASS(HexagonFixupHwLoops, "hwloopsfixup",
                "Hexagon Hardware Loops Fixup", false, false)

FunctionPass *llvm::createHexagonFixupHwLoops() {
  return new HexagonFixupHwLoops();
}

/// Returns true if the instruction is a hardware loop instruction.
static bool isHardwareLoop(const MachineInstr &MI) {
  return MI.getOpcode() == Hexagon::J2_loop0r ||
         MI.getOpcode() == Hexagon::J2_loop0i ||
         MI.getOpcode() == Hexagon::J2_loop1r ||
         MI.getOpcode() == Hexagon::J2_loop1i;
}

bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
  if (skipFunction(MF.getFunction()))
    return false;
  return fixupLoopInstrs(MF);
}

/// For Hexagon, if the loop label is to far from the
/// loop instruction then we need to set the LC0 and SA0 registers
/// explicitly instead of using LOOP(start,count).  This function
/// checks the distance, and generates register assignments if needed.
///
/// This function makes two passes over the basic blocks.  The first
/// pass computes the offset of the basic block from the start.
/// The second pass checks all the loop instructions.
bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {

// Offset of the current instruction from the start.
  unsigned InstOffset = 0;
  // Map for each basic block to it's first instruction.
  DenseMap<const MachineBasicBlock *, unsigned> BlockToInstOffset;

const HexagonInstrInfo *HII =
      static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());

// First pass - compute the offset of each basic block.
  for (const MachineBasicBlock &MBB : MF) {
    if (MBB.getAlignment() != Align(1)) {
      // Although we don't know the exact layout of the final code, we need
      // to account for alignment padding somehow. This heuristic pads each
      // aligned basic block according to the alignment value.
      InstOffset = alignTo(InstOffset, MBB.getAlignment());
    }

BlockToInstOffset[&MBB] = InstOffset;
    for (const MachineInstr &MI : MBB)
      InstOffset += HII->getSize(MI);
  }

// Second pass - check each loop instruction to see if it needs to be
  // converted.
  bool Changed = false;
  for (MachineBasicBlock &MBB : MF) {
    InstOffset = BlockToInstOffset[&MBB];

// Loop over all the instructions.
    MachineBasicBlock::iterator MII = MBB.begin();
    MachineBasicBlock::iterator MIE = MBB.end();
    while (MII != MIE) {
      unsigned InstSize = HII->getSize(*MII);
      if (MII->isMetaInstruction()) {
        ++MII;
        continue;
      }
      if (isHardwareLoop(*MII)) {
        assert(MII->getOperand(0).isMBB() &&
               "Expect a basic block as loop operand");
        MachineBasicBlock *TargetBB = MII->getOperand(0).getMBB();
        unsigned Diff = AbsoluteDifference(InstOffset,
                                           BlockToInstOffset[TargetBB]);
        if (Diff > MaxLoopRange) {
          useExtLoopInstr(MF, MII);
          MII = MBB.erase(MII);
          Changed = true;
        } else {
          ++MII;
        }
      } else {
        ++MII;
      }
      InstOffset += InstSize;
    }
  }

return Changed;
}

/// Replace loop instructions with the constant extended version.
void HexagonFixupHwLoops::useExtLoopInstr(MachineFunction &MF,
                                          MachineBasicBlock::iterator &MII) {
  const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
  MachineBasicBlock *MBB = MII->getParent();
  DebugLoc DL = MII->getDebugLoc();
  MachineInstrBuilder MIB;
  unsigned newOp;
  switch (MII->getOpcode()) {
  case Hexagon::J2_loop0r:
    newOp = Hexagon::J2_loop0rext;
    break;
  case Hexagon::J2_loop0i:
    newOp = Hexagon::J2_loop0iext;
    break;
  case Hexagon::J2_loop1r:
    newOp = Hexagon::J2_loop1rext;
    break;
  case Hexagon::J2_loop1i:
    newOp = Hexagon::J2_loop1iext;
    break;
  default:
    llvm_unreachable("Invalid Hardware Loop Instruction.");
  }
  MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));

for (unsigned i = 0; i < MII->getNumOperands(); ++i)
    MIB.add(MII->getOperand(i));
}

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Editing: HexagonFixupHwLoops.cpp

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