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📁 ..
📁 AsmParser
📄 BitTracker.cpp(35.36 KB)
📄 BitTracker.h(17.25 KB)
📁 Disassembler
📄 Hexagon.h(1004 B)
📄 Hexagon.td(17.33 KB)
📄 HexagonArch.h(1.2 KB)
📄 HexagonAsmPrinter.cpp(26.65 KB)
📄 HexagonAsmPrinter.h(2.03 KB)
📄 HexagonBitSimplify.cpp(107.45 KB)
📄 HexagonBitTracker.cpp(39.88 KB)
📄 HexagonBitTracker.h(2.5 KB)
📄 HexagonBlockRanges.cpp(15.85 KB)
📄 HexagonBlockRanges.h(6.97 KB)
📄 HexagonBranchRelaxation.cpp(7.78 KB)
📄 HexagonCFGOptimizer.cpp(8.4 KB)
📄 HexagonCallingConv.td(4.46 KB)
📄 HexagonCommonGEP.cpp(41.47 KB)
📄 HexagonConstExtenders.cpp(70.64 KB)
📄 HexagonConstPropagation.cpp(97.75 KB)
📄 HexagonCopyToCombine.cpp(32.2 KB)
📄 HexagonDepArch.h(2.04 KB)
📄 HexagonDepArch.td(1.87 KB)
📄 HexagonDepDecoders.inc(2.55 KB)
📄 HexagonDepIICHVX.td(113.05 KB)
📄 HexagonDepIICScalar.td(224.12 KB)
📄 HexagonDepITypes.h(1.51 KB)
📄 HexagonDepITypes.td(1.91 KB)
📄 HexagonDepInstrFormats.td(91.89 KB)
📄 HexagonDepInstrInfo.td(1021.44 KB)
📄 HexagonDepMapAsm2Intrin.td(255.17 KB)
📄 HexagonDepMappings.td(64.27 KB)
📄 HexagonDepMask.h(51.94 KB)
📄 HexagonDepOperands.td(12.12 KB)
📄 HexagonDepTimingClasses.h(4.69 KB)
📄 HexagonEarlyIfConv.cpp(37.36 KB)
📄 HexagonExpandCondsets.cpp(48.55 KB)
📄 HexagonFixupHwLoops.cpp(6.54 KB)
📄 HexagonFrameLowering.cpp(97.16 KB)
📄 HexagonFrameLowering.h(7.85 KB)
📄 HexagonGenExtract.cpp(8.61 KB)
📄 HexagonGenInsert.cpp(53.24 KB)
📄 HexagonGenMux.cpp(12.71 KB)
📄 HexagonGenPredicate.cpp(16.25 KB)
📄 HexagonHardwareLoops.cpp(70.32 KB)
📄 HexagonHazardRecognizer.cpp(5.85 KB)
📄 HexagonHazardRecognizer.h(3.58 KB)
📄 HexagonIICHVX.td(1.21 KB)
📄 HexagonIICScalar.td(1.34 KB)
📄 HexagonISelDAGToDAG.cpp(78.63 KB)
📄 HexagonISelDAGToDAG.h(5.88 KB)
📄 HexagonISelDAGToDAGHVX.cpp(68.26 KB)
📄 HexagonISelLowering.cpp(134.65 KB)
📄 HexagonISelLowering.h(22.5 KB)
📄 HexagonISelLoweringHVX.cpp(70.57 KB)
📄 HexagonInstrFormats.td(12.04 KB)
📄 HexagonInstrFormatsV60.td(1.03 KB)
📄 HexagonInstrFormatsV65.td(1.54 KB)
📄 HexagonInstrInfo.cpp(161.08 KB)
📄 HexagonInstrInfo.h(25.31 KB)
📄 HexagonIntrinsics.td(19.21 KB)
📄 HexagonIntrinsicsV5.td(16.8 KB)
📄 HexagonIntrinsicsV60.td(28.9 KB)
📄 HexagonLoopIdiomRecognition.cpp(79.16 KB)
📄 HexagonMCInstLower.cpp(6.25 KB)
📄 HexagonMachineFunctionInfo.cpp(507 B)
📄 HexagonMachineFunctionInfo.h(3.32 KB)
📄 HexagonMachineScheduler.cpp(34.25 KB)
📄 HexagonMachineScheduler.h(8.66 KB)
📄 HexagonMapAsm2IntrinV62.gen.td(8.71 KB)
📄 HexagonMapAsm2IntrinV65.gen.td(12.43 KB)
📄 HexagonNewValueJump.cpp(25.57 KB)
📄 HexagonOperands.td(1.62 KB)
📄 HexagonOptAddrMode.cpp(29.37 KB)
📄 HexagonOptimizeSZextends.cpp(4.74 KB)
📄 HexagonPatterns.td(142.35 KB)
📄 HexagonPatternsHVX.td(22.06 KB)
📄 HexagonPatternsV65.td(2.96 KB)
📄 HexagonPeephole.cpp(10.18 KB)
📄 HexagonPseudo.td(21.62 KB)
📄 HexagonRDFOpt.cpp(9.94 KB)
📄 HexagonRegisterInfo.cpp(12.03 KB)
📄 HexagonRegisterInfo.h(2.88 KB)
📄 HexagonRegisterInfo.td(20.42 KB)
📄 HexagonSchedule.td(2.33 KB)
📄 HexagonScheduleV5.td(1.73 KB)
📄 HexagonScheduleV55.td(1.81 KB)
📄 HexagonScheduleV60.td(4.31 KB)
📄 HexagonScheduleV62.td(1.53 KB)
📄 HexagonScheduleV65.td(1.57 KB)
📄 HexagonScheduleV66.td(1.57 KB)
📄 HexagonScheduleV67.td(1.57 KB)
📄 HexagonScheduleV67T.td(2.51 KB)
📄 HexagonSelectionDAGInfo.cpp(2.35 KB)
📄 HexagonSelectionDAGInfo.h(1.24 KB)
📄 HexagonSplitConst32AndConst64.cpp(4.15 KB)
📄 HexagonSplitDouble.cpp(37.86 KB)
📄 HexagonStoreWidening.cpp(20.47 KB)
📄 HexagonSubtarget.cpp(20.97 KB)
📄 HexagonSubtarget.h(10.59 KB)
📄 HexagonTargetMachine.cpp(16 KB)
📄 HexagonTargetMachine.h(1.77 KB)
📄 HexagonTargetObjectFile.cpp(16.8 KB)
📄 HexagonTargetObjectFile.h(2.17 KB)
📄 HexagonTargetStreamer.h(1.2 KB)
📄 HexagonTargetTransformInfo.cpp(13.11 KB)
📄 HexagonTargetTransformInfo.h(6.27 KB)
📄 HexagonVExtract.cpp(6.64 KB)
📄 HexagonVLIWPacketizer.cpp(67.01 KB)
📄 HexagonVLIWPacketizer.h(6.09 KB)
📄 HexagonVectorLoopCarriedReuse.cpp(23.99 KB)
📄 HexagonVectorPrint.cpp(7.06 KB)
📁 MCTargetDesc
📄 RDFCopy.cpp(6.37 KB)
📄 RDFCopy.h(1.69 KB)
📄 RDFDeadCode.cpp(7.5 KB)
📄 RDFDeadCode.h(2.33 KB)
📁 TargetInfo

Editing: HexagonVLIWPacketizer.h

//===- HexagonPacketizer.h - VLIW packetizer --------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H

#include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include <vector>

namespace llvm {

class HexagonInstrInfo;
class HexagonRegisterInfo;
class MachineBranchProbabilityInfo;
class MachineFunction;
class MachineInstr;
class MachineLoopInfo;
class TargetRegisterClass;

class HexagonPacketizerList : public VLIWPacketizerList {
  // Vector of instructions assigned to the packet that has just been created.
  std::vector<MachineInstr *> OldPacketMIs;

// Has the instruction been promoted to a dot-new instruction.
  bool PromotedToDotNew;

// Has the instruction been glued to allocframe.
  bool GlueAllocframeStore;

// Has the feeder instruction been glued to new value jump.
  bool GlueToNewValueJump;

// This holds the offset value, when pruning the dependences.
  int64_t ChangedOffset;

// Check if there is a dependence between some instruction already in this
  // packet and this instruction.
  bool Dependence;

// Only check for dependence if there are resources available to
  // schedule this instruction.
  bool FoundSequentialDependence;

bool MemShufDisabled = false;

// Track MIs with ignored dependence.
  std::vector<MachineInstr*> IgnoreDepMIs;

// Set to true if the packet contains an instruction that stalls with an
  // instruction from the previous packet.
  bool PacketStalls = false;

// Set to true if the packet has a duplex pair of sub-instructions.
  bool PacketHasDuplex = false;

// Set to true if the packet has a instruction that can only be executed
  // in SLOT0.
  bool PacketHasSLOT0OnlyInsn = false;

protected:
  /// A handle to the branch probability pass.
  const MachineBranchProbabilityInfo *MBPI;
  const MachineLoopInfo *MLI;

private:
  const HexagonInstrInfo *HII;
  const HexagonRegisterInfo *HRI;
  const bool Minimal;

public:
  HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
                        AAResults *AA, const MachineBranchProbabilityInfo *MBPI,
                        bool Minimal);

// initPacketizerState - initialize some internal flags.
  void initPacketizerState() override;

// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
  bool ignorePseudoInstruction(const MachineInstr &MI,
                               const MachineBasicBlock *MBB) override;

// isSoloInstruction - return true if instruction MI can not be packetized
  // with any other instruction, which means that MI itself is a packet.
  bool isSoloInstruction(const MachineInstr &MI) override;

// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
  // together.
  bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;

// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
  // and SUJ.
  bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;

bool foundLSInPacket();
  MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
  void endPacket(MachineBasicBlock *MBB,
                 MachineBasicBlock::iterator MI) override;
  bool shouldAddToPacket(const MachineInstr &MI) override;

void unpacketizeSoloInstrs(MachineFunction &MF);

protected:
  bool getmemShufDisabled() {
    return MemShufDisabled;
  };
  void setmemShufDisabled(bool val) {
    MemShufDisabled = val;
  };
  bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
                       unsigned DepReg);
  bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
                       MachineBasicBlock::iterator &MII,
                       const TargetRegisterClass *RC);
  bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
                          unsigned DepReg, MachineBasicBlock::iterator &MII,
                          const TargetRegisterClass *RC);
  void cleanUpDotCur();

bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
                       MachineBasicBlock::iterator &MII,
                       const TargetRegisterClass *RC);
  bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
                          unsigned DepReg, MachineBasicBlock::iterator &MII,
                          const TargetRegisterClass *RC);
  bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
                            unsigned DepReg, MachineBasicBlock::iterator &MII);
  bool canPromoteToNewValueStore(const MachineInstr &MI,
                                 const MachineInstr &PacketMI, unsigned DepReg);
  bool demoteToDotOld(MachineInstr &MI);
  bool useCallersSP(MachineInstr &MI);
  void useCalleesSP(MachineInstr &MI);
  bool updateOffset(SUnit *SUI, SUnit *SUJ);
  void undoChangedOffset(MachineInstr &MI);
  bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
  bool restrictingDepExistInPacket(MachineInstr&, unsigned);
  bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
  bool isCurifiable(MachineInstr &MI);
  bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);

bool isPromotedToDotNew() const {
    return PromotedToDotNew;
  }

bool tryAllocateResourcesForConstExt(bool Reserve);
  bool canReserveResourcesForConstExt();
  void reserveResourcesForConstExt();
  bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
  bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
  bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
  bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J);
  bool producesStall(const MachineInstr &MI);
  bool isPureSlot0InsnWithNoSlot1Store(const MachineInstr &MI);
};

} // end namespace llvm

#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H

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