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📄 AsmMatcherEmitter.cpp(149.98 KB)
📄 AsmWriterEmitter.cpp(46.29 KB)
📄 AsmWriterInst.cpp(7.57 KB)
📄 AsmWriterInst.h(3.83 KB)
📄 Attributes.cpp(3.12 KB)
📄 CTagsEmitter.cpp(2.52 KB)
📄 CallingConvEmitter.cpp(11.74 KB)
📄 CodeEmitterGen.cpp(22.5 KB)
📄 CodeGenDAGPatterns.cpp(168.72 KB)
📄 CodeGenDAGPatterns.h(47.85 KB)
📄 CodeGenHwModes.cpp(3.45 KB)
📄 CodeGenHwModes.h(1.84 KB)
📄 CodeGenInstruction.cpp(30.97 KB)
📄 CodeGenInstruction.h(13.7 KB)
📄 CodeGenIntrinsics.h(6.6 KB)
📄 CodeGenMapTable.cpp(23.38 KB)
📄 CodeGenRegisters.cpp(90.68 KB)
📄 CodeGenRegisters.h(29.9 KB)
📄 CodeGenSchedule.cpp(84.92 KB)
📄 CodeGenSchedule.h(23.14 KB)
📄 CodeGenTarget.cpp(32.63 KB)
📄 CodeGenTarget.h(7.22 KB)
📄 DAGISelEmitter.cpp(6.92 KB)
📄 DAGISelMatcher.cpp(13.53 KB)
📄 DAGISelMatcher.h(37.72 KB)
📄 DAGISelMatcherEmitter.cpp(37.44 KB)
📄 DAGISelMatcherGen.cpp(44.06 KB)
📄 DAGISelMatcherOpt.cpp(17.35 KB)
📄 DFAEmitter.cpp(13.11 KB)
📄 DFAEmitter.h(3.96 KB)
📄 DFAPacketizerEmitter.cpp(13.02 KB)
📄 DirectiveEmitter.cpp(20.15 KB)
📄 DisassemblerEmitter.cpp(7.02 KB)
📄 ExegesisEmitter.cpp(7.39 KB)
📄 FastISelEmitter.cpp(30.83 KB)
📄 FixedLenDecoderEmitter.cpp(90.04 KB)
📄 GICombinerEmitter.cpp(40.12 KB)
📁 GlobalISel
📄 GlobalISelEmitter.cpp(215.56 KB)
📄 InfoByHwMode.cpp(6.69 KB)
📄 InfoByHwMode.h(5.74 KB)
📄 InstrDocsEmitter.cpp(7.05 KB)
📄 InstrInfoEmitter.cpp(31.52 KB)
📄 IntrinsicEmitter.cpp(32.87 KB)
📄 OptEmitter.cpp(2.9 KB)
📄 OptEmitter.h(575 B)
📄 OptParserEmitter.cpp(15.16 KB)
📄 OptRSTEmitter.cpp(2.71 KB)
📄 PredicateExpander.cpp(17.39 KB)
📄 PredicateExpander.h(5.19 KB)
📄 PseudoLoweringEmitter.cpp(11.8 KB)
📄 RISCVCompressInstEmitter.cpp(39.23 KB)
📄 RegisterBankEmitter.cpp(12.52 KB)
📄 RegisterInfoEmitter.cpp(61.32 KB)
📄 SDNodeProperties.cpp(1.9 KB)
📄 SDNodeProperties.h(985 B)
📄 SearchableTableEmitter.cpp(26.81 KB)
📄 SequenceToOffsetTable.h(8.49 KB)
📄 SubtargetEmitter.cpp(70.77 KB)
📄 SubtargetFeatureInfo.cpp(5.72 KB)
📄 SubtargetFeatureInfo.h(4.05 KB)
📄 TableGen.cpp(9.7 KB)
📄 TableGenBackends.h(4.62 KB)
📄 Types.cpp(1.46 KB)
📄 Types.h(900 B)
📄 WebAssemblyDisassemblerEmitter.cpp(6.79 KB)
📄 WebAssemblyDisassemblerEmitter.h(980 B)
📄 X86DisassemblerShared.h(1.88 KB)
📄 X86DisassemblerTables.cpp(42.64 KB)
📄 X86DisassemblerTables.h(11.7 KB)
📄 X86EVEX2VEXTablesEmitter.cpp(8.77 KB)
📄 X86FoldTablesEmitter.cpp(26.09 KB)
📄 X86ModRMFilters.cpp(636 B)
📄 X86ModRMFilters.h(4.69 KB)
📄 X86RecognizableInstr.cpp(47.05 KB)
📄 X86RecognizableInstr.h(14.13 KB)

Editing: InfoByHwMode.cpp

//===--- InfoByHwMode.cpp -------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Classes that implement data parameterized by HW modes for instruction
// selection. Currently it is ValueTypeByHwMode (parameterized ValueType),
// and RegSizeInfoByHwMode (parameterized register/spill size and alignment
// data).
//===----------------------------------------------------------------------===//

#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

#include <set>
#include <string>

using namespace llvm;

std::string llvm::getModeName(unsigned Mode) {
  if (Mode == DefaultMode)
    return "*";
  return (Twine('m') + Twine(Mode)).str();
}

ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) {
  const HwModeSelect &MS = CGH.getHwModeSelect(R);
  for (const HwModeSelect::PairType &P : MS.Items) {
    auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))});
    assert(I.second && "Duplicate entry?");
    (void)I;
  }
}

ValueTypeByHwMode::ValueTypeByHwMode(Record *R, MVT T) : ValueTypeByHwMode(T) {
  if (R->isSubClassOf("PtrValueType"))
    PtrAddrSpace = R->getValueAsInt("AddrSpace");
}

bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const {
  assert(isValid() && T.isValid() && "Invalid type in assignment");
  bool Simple = isSimple();
  if (Simple != T.isSimple())
    return false;
  if (Simple)
    return getSimple() == T.getSimple();

return Map == T.Map;
}

bool ValueTypeByHwMode::operator< (const ValueTypeByHwMode &T) const {
  assert(isValid() && T.isValid() && "Invalid type in comparison");
  // Default order for maps.
  return Map < T.Map;
}

MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) {
  auto F = Map.find(Mode);
  if (F != Map.end())
    return F->second;
  // If Mode is not in the map, look up the default mode. If it exists,
  // make a copy of it for Mode and return it.
  auto D = Map.find(DefaultMode);
  if (D != Map.end())
    return Map.insert(std::make_pair(Mode, D->second)).first->second;
  // If default mode is not present either, use provided Type.
  return Map.insert(std::make_pair(Mode, Type)).first->second;
}

StringRef ValueTypeByHwMode::getMVTName(MVT T) {
  StringRef N = llvm::getEnumName(T.SimpleTy);
  N.consume_front("MVT::");
  return N;
}

void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
  if (isSimple()) {
    OS << getMVTName(getSimple());
    return;
  }

std::vector<const PairType*> Pairs;
  for (const auto &P : Map)
    Pairs.push_back(&P);
  llvm::sort(Pairs, deref<std::less<PairType>>());

OS << '{';
  for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
    const PairType *P = Pairs[i];
    OS << '(' << getModeName(P->first)
       << ':' << getMVTName(P->second).str() << ')';
    if (i != e-1)
      OS << ',';
  }
  OS << '}';
}

LLVM_DUMP_METHOD
void ValueTypeByHwMode::dump() const {
  dbgs() << *this << '\n';
}

ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec,
                                             const CodeGenHwModes &CGH) {
#ifndef NDEBUG
  if (!Rec->isSubClassOf("ValueType"))
    Rec->dump();
#endif
  assert(Rec->isSubClassOf("ValueType") &&
         "Record must be derived from ValueType");
  if (Rec->isSubClassOf("HwModeSelect"))
    return ValueTypeByHwMode(Rec, CGH);
  return ValueTypeByHwMode(Rec, llvm::getValueType(Rec));
}

RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) {
  RegSize = R->getValueAsInt("RegSize");
  SpillSize = R->getValueAsInt("SpillSize");
  SpillAlignment = R->getValueAsInt("SpillAlignment");
}

bool RegSizeInfo::operator< (const RegSizeInfo &I) const {
  return std::tie(RegSize, SpillSize, SpillAlignment) <
         std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
}

bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const {
  return RegSize <= I.RegSize &&
         SpillAlignment && I.SpillAlignment % SpillAlignment == 0 &&
         SpillSize <= I.SpillSize;
}

void RegSizeInfo::writeToStream(raw_ostream &OS) const {
  OS << "[R=" << RegSize << ",S=" << SpillSize
     << ",A=" << SpillAlignment << ']';
}

RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R,
      const CodeGenHwModes &CGH) {
  const HwModeSelect &MS = CGH.getHwModeSelect(R);
  for (const HwModeSelect::PairType &P : MS.Items) {
    auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)});
    assert(I.second && "Duplicate entry?");
    (void)I;
  }
}

bool RegSizeInfoByHwMode::operator< (const RegSizeInfoByHwMode &I) const {
  unsigned M0 = Map.begin()->first;
  return get(M0) < I.get(M0);
}

bool RegSizeInfoByHwMode::operator== (const RegSizeInfoByHwMode &I) const {
  unsigned M0 = Map.begin()->first;
  return get(M0) == I.get(M0);
}

bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const {
  unsigned M0 = Map.begin()->first;
  return get(M0).isSubClassOf(I.get(M0));
}

bool RegSizeInfoByHwMode::hasStricterSpillThan(const RegSizeInfoByHwMode &I)
      const {
  unsigned M0 = Map.begin()->first;
  const RegSizeInfo &A0 = get(M0);
  const RegSizeInfo &B0 = I.get(M0);
  return std::tie(A0.SpillSize, A0.SpillAlignment) >
         std::tie(B0.SpillSize, B0.SpillAlignment);
}

void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
  typedef typename decltype(Map)::value_type PairType;
  std::vector<const PairType*> Pairs;
  for (const auto &P : Map)
    Pairs.push_back(&P);
  llvm::sort(Pairs, deref<std::less<PairType>>());

OS << '{';
  for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
    const PairType *P = Pairs[i];
    OS << '(' << getModeName(P->first) << ':' << P->second << ')';
    if (i != e-1)
      OS << ',';
  }
  OS << '}';
}

EncodingInfoByHwMode::EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH) {
  const HwModeSelect &MS = CGH.getHwModeSelect(R);
  for (const HwModeSelect::PairType &P : MS.Items) {
    assert(P.second && P.second->isSubClassOf("InstructionEncoding") &&
           "Encoding must subclass InstructionEncoding");
    auto I = Map.insert({P.first, P.second});
    assert(I.second && "Duplicate entry?");
    (void)I;
  }
}

namespace llvm {
  raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
    T.writeToStream(OS);
    return OS;
  }

raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) {
    T.writeToStream(OS);
    return OS;
  }

raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
    T.writeToStream(OS);
    return OS;
  }
}

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Editing: InfoByHwMode.cpp

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