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AsmMatcherEmitter.cpp
(149.98 KB)
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AsmWriterEmitter.cpp
(46.29 KB)
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AsmWriterInst.cpp
(7.57 KB)
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AsmWriterInst.h
(3.83 KB)
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Attributes.cpp
(3.12 KB)
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CTagsEmitter.cpp
(2.52 KB)
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CallingConvEmitter.cpp
(11.74 KB)
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CodeEmitterGen.cpp
(22.5 KB)
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CodeGenDAGPatterns.cpp
(168.72 KB)
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CodeGenDAGPatterns.h
(47.85 KB)
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CodeGenHwModes.cpp
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CodeGenHwModes.h
(1.84 KB)
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CodeGenInstruction.cpp
(30.97 KB)
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CodeGenInstruction.h
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CodeGenIntrinsics.h
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CodeGenMapTable.cpp
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CodeGenRegisters.cpp
(90.68 KB)
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CodeGenRegisters.h
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CodeGenSchedule.cpp
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CodeGenSchedule.h
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CodeGenTarget.cpp
(32.63 KB)
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CodeGenTarget.h
(7.22 KB)
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DAGISelEmitter.cpp
(6.92 KB)
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DAGISelMatcher.cpp
(13.53 KB)
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DAGISelMatcher.h
(37.72 KB)
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DAGISelMatcherEmitter.cpp
(37.44 KB)
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DAGISelMatcherGen.cpp
(44.06 KB)
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DAGISelMatcherOpt.cpp
(17.35 KB)
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DFAEmitter.cpp
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DFAEmitter.h
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DFAPacketizerEmitter.cpp
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DirectiveEmitter.cpp
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DisassemblerEmitter.cpp
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ExegesisEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
(90.04 KB)
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GICombinerEmitter.cpp
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GlobalISel
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GlobalISelEmitter.cpp
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InfoByHwMode.cpp
(6.69 KB)
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InfoByHwMode.h
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InstrDocsEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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OptEmitter.cpp
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OptEmitter.h
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OptParserEmitter.cpp
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OptRSTEmitter.cpp
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PredicateExpander.cpp
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PredicateExpander.h
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PseudoLoweringEmitter.cpp
(11.8 KB)
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RISCVCompressInstEmitter.cpp
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RegisterBankEmitter.cpp
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RegisterInfoEmitter.cpp
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SDNodeProperties.cpp
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SDNodeProperties.h
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SearchableTableEmitter.cpp
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SequenceToOffsetTable.h
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SubtargetEmitter.cpp
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SubtargetFeatureInfo.cpp
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SubtargetFeatureInfo.h
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TableGen.cpp
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TableGenBackends.h
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Types.cpp
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Types.h
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WebAssemblyDisassemblerEmitter.cpp
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WebAssemblyDisassemblerEmitter.h
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X86DisassemblerShared.h
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X86DisassemblerTables.cpp
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X86DisassemblerTables.h
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X86EVEX2VEXTablesEmitter.cpp
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X86FoldTablesEmitter.cpp
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X86ModRMFilters.cpp
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X86ModRMFilters.h
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X86RecognizableInstr.cpp
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X86RecognizableInstr.h
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Editing: InfoByHwMode.h
//===--- InfoByHwMode.h -----------------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // Classes that implement data parameterized by HW modes for instruction // selection. Currently it is ValueTypeByHwMode (parameterized ValueType), // and RegSizeInfoByHwMode (parameterized register/spill size and alignment // data). //===----------------------------------------------------------------------===// #ifndef LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H #define LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H #include "CodeGenHwModes.h" #include "llvm/Support/MachineValueType.h" #include <map> #include <set> #include <string> #include <vector> namespace llvm { struct CodeGenHwModes; class Record; class raw_ostream; template <typename InfoT> struct InfoByHwMode; std::string getModeName(unsigned Mode); enum : unsigned { DefaultMode = CodeGenHwModes::DefaultMode, }; template <typename InfoT> std::vector<unsigned> union_modes(const InfoByHwMode<InfoT> &A, const InfoByHwMode<InfoT> &B) { std::vector<unsigned> V; std::set<unsigned> U; for (const auto &P : A) U.insert(P.first); for (const auto &P : B) U.insert(P.first); // Make sure that the default mode is last on the list. bool HasDefault = false; for (unsigned M : U) if (M != DefaultMode) V.push_back(M); else HasDefault = true; if (HasDefault) V.push_back(DefaultMode); return V; } template <typename InfoT> struct InfoByHwMode { typedef std::map<unsigned,InfoT> MapType; typedef typename MapType::value_type PairType; typedef typename MapType::iterator iterator; typedef typename MapType::const_iterator const_iterator; InfoByHwMode() = default; InfoByHwMode(const MapType &M) : Map(M) {} LLVM_ATTRIBUTE_ALWAYS_INLINE iterator begin() { return Map.begin(); } LLVM_ATTRIBUTE_ALWAYS_INLINE iterator end() { return Map.end(); } LLVM_ATTRIBUTE_ALWAYS_INLINE const_iterator begin() const { return Map.begin(); } LLVM_ATTRIBUTE_ALWAYS_INLINE const_iterator end() const { return Map.end(); } LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const { return Map.empty(); } LLVM_ATTRIBUTE_ALWAYS_INLINE bool hasMode(unsigned M) const { return Map.find(M) != Map.end(); } LLVM_ATTRIBUTE_ALWAYS_INLINE bool hasDefault() const { return hasMode(DefaultMode); } InfoT &get(unsigned Mode) { if (!hasMode(Mode)) { assert(hasMode(DefaultMode)); Map.insert({Mode, Map.at(DefaultMode)}); } return Map.at(Mode); } const InfoT &get(unsigned Mode) const { auto F = Map.find(Mode); if (Mode != DefaultMode && F == Map.end()) F = Map.find(DefaultMode); assert(F != Map.end()); return F->second; } LLVM_ATTRIBUTE_ALWAYS_INLINE bool isSimple() const { return Map.size() == 1 && Map.begin()->first == DefaultMode; } LLVM_ATTRIBUTE_ALWAYS_INLINE InfoT getSimple() const { assert(isSimple()); return Map.begin()->second; } void makeSimple(unsigned Mode) { assert(hasMode(Mode) || hasDefault()); InfoT I = get(Mode); Map.clear(); Map.insert(std::make_pair(DefaultMode, I)); } MapType Map; }; struct ValueTypeByHwMode : public InfoByHwMode<MVT> { ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH); ValueTypeByHwMode(Record *R, MVT T); ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); } ValueTypeByHwMode() = default; bool operator== (const ValueTypeByHwMode &T) const; bool operator< (const ValueTypeByHwMode &T) const; bool isValid() const { return !Map.empty(); } MVT getType(unsigned Mode) const { return get(Mode); } MVT &getOrCreateTypeForMode(unsigned Mode, MVT Type); static StringRef getMVTName(MVT T); void writeToStream(raw_ostream &OS) const; void dump() const; unsigned PtrAddrSpace = std::numeric_limits<unsigned>::max(); bool isPointer() const { return PtrAddrSpace != std::numeric_limits<unsigned>::max(); } }; ValueTypeByHwMode getValueTypeByHwMode(Record *Rec, const CodeGenHwModes &CGH); struct RegSizeInfo { unsigned RegSize; unsigned SpillSize; unsigned SpillAlignment; RegSizeInfo(Record *R, const CodeGenHwModes &CGH); RegSizeInfo() = default; bool operator< (const RegSizeInfo &I) const; bool operator== (const RegSizeInfo &I) const { return std::tie(RegSize, SpillSize, SpillAlignment) == std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); } bool operator!= (const RegSizeInfo &I) const { return !(*this == I); } bool isSubClassOf(const RegSizeInfo &I) const; void writeToStream(raw_ostream &OS) const; }; struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> { RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH); RegSizeInfoByHwMode() = default; bool operator< (const RegSizeInfoByHwMode &VI) const; bool operator== (const RegSizeInfoByHwMode &VI) const; bool operator!= (const RegSizeInfoByHwMode &VI) const { return !(*this == VI); } bool isSubClassOf(const RegSizeInfoByHwMode &I) const; bool hasStricterSpillThan(const RegSizeInfoByHwMode &I) const; void writeToStream(raw_ostream &OS) const; }; raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T); raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T); raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T); struct EncodingInfoByHwMode : public InfoByHwMode<Record*> { EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH); EncodingInfoByHwMode() = default; }; } // namespace llvm #endif // LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
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