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📄 AArch64.cpp(29.01 KB)
📄 AArch64.h(6.99 KB)
📄 AMDGPU.cpp(15.27 KB)
📄 AMDGPU.h(11.06 KB)
📄 ARC.cpp(857 B)
📄 ARC.h(2.44 KB)
📄 ARM.cpp(42.48 KB)
📄 ARM.h(8.67 KB)
📄 AVR.cpp(12.02 KB)
📄 AVR.h(5.74 KB)
📄 BPF.cpp(1.75 KB)
📄 BPF.h(3.11 KB)
📄 Hexagon.cpp(7.02 KB)
📄 Hexagon.h(4.49 KB)
📄 Lanai.cpp(2.31 KB)
📄 Lanai.h(3.09 KB)
📄 Le64.cpp(1.38 KB)
📄 Le64.h(1.99 KB)
📄 MSP430.cpp(1.14 KB)
📄 MSP430.h(2.99 KB)
📄 Mips.cpp(9.62 KB)
📄 Mips.h(13.84 KB)
📄 NVPTX.cpp(8.97 KB)
📄 NVPTX.h(5.28 KB)
📄 OSTargets.cpp(7.11 KB)
📄 OSTargets.h(29.36 KB)
📄 PNaCl.cpp(1001 B)
📄 PNaCl.h(2.78 KB)
📄 PPC.cpp(21.1 KB)
📄 PPC.h(17.89 KB)
📄 RISCV.cpp(6.88 KB)
📄 RISCV.h(4.14 KB)
📄 SPIR.cpp(1.2 KB)
📄 SPIR.h(4.54 KB)
📄 Sparc.cpp(9.86 KB)
📄 Sparc.h(7.06 KB)
📄 SystemZ.cpp(5.16 KB)
📄 SystemZ.h(4.88 KB)
📄 TCE.cpp(1.17 KB)
📄 TCE.h(3.99 KB)
📄 VE.cpp(1.43 KB)
📄 VE.h(5.14 KB)
📄 WebAssembly.cpp(8.19 KB)
📄 WebAssembly.h(5.6 KB)
📄 X86.cpp(48.61 KB)
📄 X86.h(27.36 KB)
📄 XCore.cpp(1.42 KB)
📄 XCore.h(2.61 KB)

Editing: Lanai.cpp

//===--- Lanai.cpp - Implement Lanai target feature support ---------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements Lanai TargetInfo objects.
//
//===----------------------------------------------------------------------===//

#include "Lanai.h"
#include "clang/Basic/MacroBuilder.h"
#include "llvm/ADT/StringSwitch.h"

using namespace clang;
using namespace clang::targets;

const char *const LanaiTargetInfo::GCCRegNames[] = {
    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",  "r8",  "r9",  "r10",
    "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21",
    "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
};

ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const {
  return llvm::makeArrayRef(GCCRegNames);
}

const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = {
    {{"pc"}, "r2"},   {{"sp"}, "r4"},   {{"fp"}, "r5"},   {{"rv"}, "r8"},
    {{"rr1"}, "r10"}, {{"rr2"}, "r11"}, {{"rca"}, "r15"},
};

ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const {
  return llvm::makeArrayRef(GCCRegAliases);
}

bool LanaiTargetInfo::isValidCPUName(StringRef Name) const {
  return llvm::StringSwitch<bool>(Name).Case("v11", true).Default(false);
}
void LanaiTargetInfo::fillValidCPUList(
    SmallVectorImpl<StringRef> &Values) const {
  Values.emplace_back("v11");
}

bool LanaiTargetInfo::setCPU(const std::string &Name) {
  CPU = llvm::StringSwitch<CPUKind>(Name).Case("v11", CK_V11).Default(CK_NONE);

return CPU != CK_NONE;
}

bool LanaiTargetInfo::hasFeature(StringRef Feature) const {
  return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false);
}

void LanaiTargetInfo::getTargetDefines(const LangOptions &Opts,
                                       MacroBuilder &Builder) const {
  // Define __lanai__ when building for target lanai.
  Builder.defineMacro("__lanai__");

// Set define for the CPU specified.
  switch (CPU) {
  case CK_V11:
    Builder.defineMacro("__LANAI_V11__");
    break;
  case CK_NONE:
    llvm_unreachable("Unhandled target CPU");
  }
}

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Editing: Lanai.cpp

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