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AArch64.cpp
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AArch64.h
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AMDGPU.cpp
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AMDGPU.h
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ARC.cpp
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ARC.h
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ARM.cpp
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ARM.h
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AVR.cpp
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AVR.h
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BPF.cpp
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BPF.h
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Hexagon.cpp
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Hexagon.h
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Lanai.cpp
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Lanai.h
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Le64.cpp
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Le64.h
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MSP430.cpp
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MSP430.h
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Mips.cpp
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Mips.h
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NVPTX.cpp
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NVPTX.h
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OSTargets.cpp
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OSTargets.h
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PNaCl.cpp
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PNaCl.h
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PPC.cpp
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PPC.h
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RISCV.cpp
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RISCV.h
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SPIR.cpp
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SPIR.h
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Sparc.cpp
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Sparc.h
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SystemZ.cpp
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SystemZ.h
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TCE.cpp
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TCE.h
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VE.cpp
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VE.h
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WebAssembly.cpp
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WebAssembly.h
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X86.cpp
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X86.h
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XCore.cpp
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XCore.h
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Editing: Lanai.h
//===--- Lanai.h - Declare Lanai target feature support ---------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file declares Lanai TargetInfo objects. // //===----------------------------------------------------------------------===// #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_LANAI_H #define LLVM_CLANG_LIB_BASIC_TARGETS_LANAI_H #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/ADT/Triple.h" #include "llvm/Support/Compiler.h" namespace clang { namespace targets { class LLVM_LIBRARY_VISIBILITY LanaiTargetInfo : public TargetInfo { // Class for Lanai (32-bit). // The CPU profiles supported by the Lanai backend enum CPUKind { CK_NONE, CK_V11, } CPU; static const TargetInfo::GCCRegAlias GCCRegAliases[]; static const char *const GCCRegNames[]; public: LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) : TargetInfo(Triple) { // Description string has to be kept in sync with backend. resetDataLayout("E" // Big endian "-m:e" // ELF name manging "-p:32:32" // 32 bit pointers, 32 bit aligned "-i64:64" // 64 bit integers, 64 bit aligned "-a:0:32" // 32 bit alignment of objects of aggregate type "-n32" // 32 bit native integer width "-S64" // 64 bit natural stack alignment ); // Setting RegParmMax equal to what mregparm was set to in the old // toolchain RegParmMax = 4; // Set the default CPU to V11 CPU = CK_V11; // Temporary approach to make everything at least word-aligned and allow for // safely casting between pointers with different alignment requirements. // TODO: Remove this when there are no more cast align warnings on the // firmware. MinGlobalAlign = 32; } void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override; bool isValidCPUName(StringRef Name) const override; void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; bool setCPU(const std::string &Name) override; bool hasFeature(StringRef Feature) const override; ArrayRef<const char *> getGCCRegNames() const override; ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; BuiltinVaListKind getBuiltinVaListKind() const override { return TargetInfo::VoidPtrBuiltinVaList; } ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override { return false; } const char *getClobbers() const override { return ""; } bool hasExtIntType() const override { return true; } }; } // namespace targets } // namespace clang #endif // LLVM_CLANG_LIB_BASIC_TARGETS_LANAI_H
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