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usr / src / contrib / llvm-project / llvm / lib / Target / Lanai /

📁 ..
📁 AsmParser
📁 Disassembler
📄 Lanai.h(1.4 KB)
📄 Lanai.td(1.71 KB)
📄 LanaiAluCode.h(3.55 KB)
📄 LanaiAsmPrinter.cpp(8.15 KB)
📄 LanaiCallingConv.td(1.76 KB)
📄 LanaiCondCode.h(2.9 KB)
📄 LanaiDelaySlotFiller.cpp(8.89 KB)
📄 LanaiFrameLowering.cpp(8 KB)
📄 LanaiFrameLowering.h(1.91 KB)
📄 LanaiISelDAGToDAG.cpp(11.67 KB)
📄 LanaiISelLowering.cpp(55.19 KB)
📄 LanaiISelLowering.h(5.99 KB)
📄 LanaiInstrFormats.td(20.83 KB)
📄 LanaiInstrInfo.cpp(27.4 KB)
📄 LanaiInstrInfo.h(7.02 KB)
📄 LanaiInstrInfo.td(30.89 KB)
📄 LanaiMCInstLower.cpp(4.52 KB)
📄 LanaiMCInstLower.h(1.43 KB)
📄 LanaiMachineFunctionInfo.cpp(469 B)
📄 LanaiMachineFunctionInfo.h(1.95 KB)
📄 LanaiMemAluCombiner.cpp(13.52 KB)
📄 LanaiRegisterInfo.cpp(8.54 KB)
📄 LanaiRegisterInfo.h(1.78 KB)
📄 LanaiRegisterInfo.td(2.2 KB)
📄 LanaiSchedule.td(2.25 KB)
📄 LanaiSelectionDAGInfo.cpp(1.1 KB)
📄 LanaiSelectionDAGInfo.h(1.32 KB)
📄 LanaiSubtarget.cpp(1.66 KB)
📄 LanaiSubtarget.h(2.44 KB)
📄 LanaiTargetMachine.cpp(3.92 KB)
📄 LanaiTargetMachine.h(1.9 KB)
📄 LanaiTargetObjectFile.cpp(4.8 KB)
📄 LanaiTargetObjectFile.h(1.78 KB)
📄 LanaiTargetTransformInfo.h(4.2 KB)
📁 MCTargetDesc
📁 TargetInfo

Editing: LanaiSchedule.td

//=-LanaiSchedule.td - Lanai Scheduling Definitions --*- tablegen -*-=========//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

def ALU_FU  : FuncUnit;
def LDST_FU : FuncUnit;

def IIC_ALU  : InstrItinClass;
def IIC_LD   : InstrItinClass;
def IIC_ST   : InstrItinClass;
def IIC_LDSW : InstrItinClass;
def IIC_STSW : InstrItinClass;

def LanaiItinerary : ProcessorItineraries<[ALU_FU, LDST_FU],[],[
  InstrItinData<IIC_LD,   [InstrStage<1, [LDST_FU]>]>,
  InstrItinData<IIC_ST,   [InstrStage<1, [LDST_FU]>]>,
  InstrItinData<IIC_LDSW, [InstrStage<2, [LDST_FU]>]>,
  InstrItinData<IIC_STSW, [InstrStage<2, [LDST_FU]>]>,
  InstrItinData<IIC_ALU,  [InstrStage<1, [ALU_FU]>]>
]>;

def LanaiSchedModel : SchedMachineModel {
  // Cycles for loads to access the cache [default = -1]
  let LoadLatency = 2;

// Max micro-ops that can be buffered for optimized loop dispatch/execution.
  // [default = -1]
  let LoopMicroOpBufferSize = 0;

// Allow scheduler to assign default model to any unrecognized opcodes.
  // [default = 1]
  let CompleteModel = 0;

// Max micro-ops that may be scheduled per cycle. [default = 1]
  let IssueWidth = 1;

// Extra cycles for a mispredicted branch. [default = -1]
  let MispredictPenalty = 10;

// Enable Post RegAlloc Scheduler pass. [default = 0]
  let PostRAScheduler = 0;

// Max micro-ops that can be buffered. [default = -1]
  let MicroOpBufferSize = 0;

// Per-cycle resources tables. [default = NoItineraries]
  let Itineraries = LanaiItinerary;
}

def ALU : ProcResource<1> { let BufferSize = 0; }
def LdSt : ProcResource<1> { let BufferSize = 0; }

def WriteLD   : SchedWrite;
def WriteST   : SchedWrite;
def WriteLDSW : SchedWrite;
def WriteSTSW : SchedWrite;
def WriteALU  : SchedWrite;

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Editing: LanaiSchedule.td

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