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📁 GlobalISel
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📄 IndirectThunks.h(3.85 KB)
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📄 LatencyPriorityQueue.h(3.09 KB)
📄 LazyMachineBlockFrequencyInfo.h(2.82 KB)
📄 LexicalScopes.h(10.06 KB)
📄 LinkAllAsmWriterComponents.h(1.34 KB)
📄 LinkAllCodegenComponents.h(2.18 KB)
📄 LiveInterval.h(37.24 KB)
📄 LiveIntervalCalc.h(2.91 KB)
📄 LiveIntervalUnion.h(6.93 KB)
📄 LiveIntervals.h(19.86 KB)
📄 LivePhysRegs.h(7.51 KB)
📄 LiveRangeCalc.h(11.49 KB)
📄 LiveRangeEdit.h(10.45 KB)
📄 LiveRegMatrix.h(6.18 KB)
📄 LiveRegUnits.h(6.24 KB)
📄 LiveStacks.h(3.35 KB)
📄 LiveVariables.h(12.98 KB)
📄 LoopTraversal.h(4.38 KB)
📄 LowLevelType.h(1.28 KB)
📄 MBFIWrapper.h(1.58 KB)
📄 MIRFormatter.h(3.13 KB)
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📄 MIRPrinter.h(1.73 KB)
📄 MIRYamlMapping.h(23.95 KB)
📄 MachORelocation.h(2.19 KB)
📄 MachineBasicBlock.h(42.95 KB)
📄 MachineBlockFrequencyInfo.h(3.21 KB)
📄 MachineBranchProbabilityInfo.h(2.69 KB)
📄 MachineCombinerPattern.h(3.5 KB)
📄 MachineConstantPool.h(5.25 KB)
📄 MachineDominanceFrontier.h(2.93 KB)
📄 MachineDominators.h(9.59 KB)
📄 MachineFrameInfo.h(34.84 KB)
📄 MachineFunction.h(42.94 KB)
📄 MachineFunctionPass.h(2.93 KB)
📄 MachineInstr.h(73.72 KB)
📄 MachineInstrBuilder.h(22.84 KB)
📄 MachineInstrBundle.h(10.16 KB)
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📄 MachineJumpTableInfo.h(4.66 KB)
📄 MachineLoopInfo.h(7.3 KB)
📄 MachineLoopUtils.h(1.74 KB)
📄 MachineMemOperand.h(12.69 KB)
📄 MachineModuleInfo.h(9.88 KB)
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📄 MachineOptimizationRemarkEmitter.h(8.99 KB)
📄 MachineOutliner.h(8.04 KB)
📄 MachinePassRegistry.h(6.1 KB)
📄 MachinePipeliner.h(21.17 KB)
📄 MachinePostDominators.h(2.93 KB)
📄 MachineRegionInfo.h(5.93 KB)
📄 MachineRegisterInfo.h(46.75 KB)
📄 MachineSSAUpdater.h(4.37 KB)
📄 MachineScheduler.h(36.6 KB)
📄 MachineSizeOpts.h(1.86 KB)
📄 MachineTraceMetrics.h(17.17 KB)
📄 MacroFusion.h(1.96 KB)
📄 ModuloSchedule.h(15.8 KB)
📄 NonRelocatableStringpool.h(2.9 KB)
📁 PBQP
📄 PBQPRAConstraint.h(1.83 KB)
📄 ParallelCG.h(1.66 KB)
📄 Passes.h(18.96 KB)
📄 PreISelIntrinsicLowering.h(944 B)
📄 PseudoSourceValue.h(6.21 KB)
📄 RDFGraph.h(33.73 KB)
📄 RDFLiveness.h(5.01 KB)
📄 RDFRegisters.h(6.51 KB)
📄 ReachingDefAnalysis.h(10.68 KB)
📄 RegAllocPBQP.h(16.47 KB)
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📄 Register.h(5.61 KB)
📄 RegisterClassInfo.h(4.86 KB)
📄 RegisterPressure.h(21.04 KB)
📄 RegisterScavenging.h(8.73 KB)
📄 RegisterUsageInfo.h(2.3 KB)
📄 ResourcePriorityQueue.h(4.19 KB)
📄 RuntimeLibcalls.h(3.05 KB)
📄 SDNodeProperties.td(1.57 KB)
📄 ScheduleDAG.h(28.92 KB)
📄 ScheduleDAGInstrs.h(15.49 KB)
📄 ScheduleDAGMutation.h(1021 B)
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📄 SelectionDAG.h(89.12 KB)
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📄 SelectionDAGISel.h(13.48 KB)
📄 SelectionDAGNodes.h(91.77 KB)
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📄 SlotIndexes.h(24.12 KB)
📄 Spiller.h(1.16 KB)
📄 StackMaps.h(11.45 KB)
📄 StackProtector.h(4.1 KB)
📄 SwiftErrorValueTracking.h(3.87 KB)
📄 SwitchLoweringUtils.h(9.51 KB)
📄 TailDuplicator.h(5.54 KB)
📄 TargetCallingConv.h(8.26 KB)
📄 TargetFrameLowering.h(19.21 KB)
📄 TargetInstrInfo.h(84.48 KB)
📄 TargetLowering.h(194.17 KB)
📄 TargetLoweringObjectFileImpl.h(11.63 KB)
📄 TargetOpcodes.h(1.37 KB)
📄 TargetPassConfig.h(17.9 KB)
📄 TargetRegisterInfo.h(48.65 KB)
📄 TargetSchedule.h(7.75 KB)
📄 TargetSubtargetInfo.h(12.53 KB)
📄 UnreachableBlockElim.h(1.39 KB)
📄 ValueTypes.h(17.2 KB)
📄 ValueTypes.td(11.42 KB)
📄 VirtRegMap.h(6.37 KB)
📄 WasmEHFuncInfo.h(1.92 KB)
📄 WinEHFuncInfo.h(4.01 KB)

Editing: LivePhysRegs.h

//===- llvm/CodeGen/LivePhysRegs.h - Live Physical Register Set -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file
/// This file implements the LivePhysRegs utility for tracking liveness of
/// physical registers. This can be used for ad-hoc liveness tracking after
/// register allocation. You can start with the live-ins/live-outs at the
/// beginning/end of a block and update the information while walking the
/// instructions inside the block. This implementation tracks the liveness on a
/// sub-register granularity.
///
/// We assume that the high bits of a physical super-register are not preserved
/// unless the instruction has an implicit-use operand reading the super-
/// register.
///
/// X86 Example:
/// %ymm0 = ...
/// %xmm0 = ... (Kills %xmm0, all %xmm0s sub-registers, and %ymm0)
///
/// %ymm0 = ...
/// %xmm0 = ..., implicit %ymm0 (%ymm0 and all its sub-registers are alive)
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_LIVEPHYSREGS_H
#define LLVM_CODEGEN_LIVEPHYSREGS_H

#include "llvm/ADT/SparseSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include <cassert>
#include <utility>

namespace llvm {

class MachineInstr;
class MachineOperand;
class MachineRegisterInfo;
class raw_ostream;

/// A set of physical registers with utility functions to track liveness
/// when walking backward/forward through a basic block.
class LivePhysRegs {
  const TargetRegisterInfo *TRI = nullptr;
  using RegisterSet = SparseSet<MCPhysReg, identity<MCPhysReg>>;
  RegisterSet LiveRegs;

public:
  /// Constructs an unitialized set. init() needs to be called to initialize it.
  LivePhysRegs() = default;

/// Constructs and initializes an empty set.
  LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) {
    LiveRegs.setUniverse(TRI.getNumRegs());
  }

LivePhysRegs(const LivePhysRegs&) = delete;
  LivePhysRegs &operator=(const LivePhysRegs&) = delete;

/// (re-)initializes and clears the set.
  void init(const TargetRegisterInfo &TRI) {
    this->TRI = &TRI;
    LiveRegs.clear();
    LiveRegs.setUniverse(TRI.getNumRegs());
  }

/// Clears the set.
  void clear() { LiveRegs.clear(); }

/// Returns true if the set is empty.
  bool empty() const { return LiveRegs.empty(); }

/// Adds a physical register and all its sub-registers to the set.
  void addReg(MCPhysReg Reg) {
    assert(TRI && "LivePhysRegs is not initialized.");
    assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
    for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
         SubRegs.isValid(); ++SubRegs)
      LiveRegs.insert(*SubRegs);
  }

/// Removes a physical register, all its sub-registers, and all its
  /// super-registers from the set.
  void removeReg(MCPhysReg Reg) {
    assert(TRI && "LivePhysRegs is not initialized.");
    assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
    for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R)
      LiveRegs.erase(*R);
  }

/// Removes physical registers clobbered by the regmask operand \p MO.
  void removeRegsInMask(const MachineOperand &MO,
        SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
        nullptr);

/// Returns true if register \p Reg is contained in the set. This also
  /// works if only the super register of \p Reg has been defined, because
  /// addReg() always adds all sub-registers to the set as well.
  /// Note: Returns false if just some sub registers are live, use available()
  /// when searching a free register.
  bool contains(MCPhysReg Reg) const { return LiveRegs.count(Reg); }

/// Returns true if register \p Reg and no aliasing register is in the set.
  bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;

/// Remove defined registers and regmask kills from the set.
  void removeDefs(const MachineInstr &MI);

/// Add uses to the set.
  void addUses(const MachineInstr &MI);

/// Simulates liveness when stepping backwards over an instruction(bundle).
  /// Remove Defs, add uses. This is the recommended way of calculating
  /// liveness.
  void stepBackward(const MachineInstr &MI);

/// Simulates liveness when stepping forward over an instruction(bundle).
  /// Remove killed-uses, add defs. This is the not recommended way, because it
  /// depends on accurate kill flags. If possible use stepBackward() instead of
  /// this function. The clobbers set will be the list of registers either
  /// defined or clobbered by a regmask.  The operand will identify whether this
  /// is a regmask or register operand.
  void stepForward(const MachineInstr &MI,
        SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);

/// Adds all live-in registers of basic block \p MBB.
  /// Live in registers are the registers in the blocks live-in list and the
  /// pristine registers.
  void addLiveIns(const MachineBasicBlock &MBB);

/// Adds all live-out registers of basic block \p MBB.
  /// Live out registers are the union of the live-in registers of the successor
  /// blocks and pristine registers. Live out registers of the end block are the
  /// callee saved registers.
  /// If a register is not added by this method, it is guaranteed to not be
  /// live out from MBB, although a sub-register may be. This is true
  /// both before and after regalloc.
  void addLiveOuts(const MachineBasicBlock &MBB);

/// Adds all live-out registers of basic block \p MBB but skips pristine
  /// registers.
  void addLiveOutsNoPristines(const MachineBasicBlock &MBB);

using const_iterator = RegisterSet::const_iterator;

const_iterator begin() const { return LiveRegs.begin(); }
  const_iterator end() const { return LiveRegs.end(); }

/// Prints the currently live registers to \p OS.
  void print(raw_ostream &OS) const;

/// Dumps the currently live registers to the debug output.
  void dump() const;

private:
  /// Adds live-in registers from basic block \p MBB, taking associated
  /// lane masks into consideration.
  void addBlockLiveIns(const MachineBasicBlock &MBB);

/// Adds pristine registers. Pristine registers are callee saved registers
  /// that are unused in the function.
  void addPristines(const MachineFunction &MF);
};

inline raw_ostream &operator<<(raw_ostream &OS, const LivePhysRegs& LR) {
  LR.print(OS);
  return OS;
}

/// Computes registers live-in to \p MBB assuming all of its successors
/// live-in lists are up-to-date. Puts the result into the given LivePhysReg
/// instance \p LiveRegs.
void computeLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB);

/// Recomputes dead and kill flags in \p MBB.
void recomputeLivenessFlags(MachineBasicBlock &MBB);

/// Adds registers contained in \p LiveRegs to the block live-in list of \p MBB.
/// Does not add reserved registers.
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs);

/// Convenience function combining computeLiveIns() and addLiveIns().
void computeAndAddLiveIns(LivePhysRegs &LiveRegs,
                          MachineBasicBlock &MBB);

/// Convenience function for recomputing live-in's for \p MBB.
static inline void recomputeLiveIns(MachineBasicBlock &MBB) {
  LivePhysRegs LPR;
  MBB.clearLiveIns();
  computeAndAddLiveIns(LPR, MBB);
}

} // end namespace llvm

#endif // LLVM_CODEGEN_LIVEPHYSREGS_H

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