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📄 ConstantPools.cpp(3.72 KB)
📄 ELFObjectWriter.cpp(51.58 KB)
📄 MCAsmBackend.cpp(4.01 KB)
📄 MCAsmInfo.cpp(4.44 KB)
📄 MCAsmInfoCOFF.cpp(2.17 KB)
📄 MCAsmInfoDarwin.cpp(3.01 KB)
📄 MCAsmInfoELF.cpp(1.05 KB)
📄 MCAsmInfoWasm.cpp(853 B)
📄 MCAsmInfoXCOFF.cpp(1.63 KB)
📄 MCAsmMacro.cpp(1.12 KB)
📄 MCAsmStreamer.cpp(68.69 KB)
📄 MCAssembler.cpp(42.61 KB)
📄 MCCodeEmitter.cpp(515 B)
📄 MCCodeView.cpp(25.49 KB)
📄 MCContext.cpp(31.94 KB)
📁 MCDisassembler
📄 MCDwarf.cpp(71.58 KB)
📄 MCELFObjectTargetWriter.cpp(1.29 KB)
📄 MCELFStreamer.cpp(24.89 KB)
📄 MCExpr.cpp(34.06 KB)
📄 MCFragment.cpp(15.28 KB)
📄 MCInst.cpp(2.6 KB)
📄 MCInstPrinter.cpp(7.87 KB)
📄 MCInstrAnalysis.cpp(1.2 KB)
📄 MCInstrDesc.cpp(1.96 KB)
📄 MCInstrInfo.cpp(1.03 KB)
📄 MCLabel.cpp(772 B)
📄 MCLinkerOptimizationHint.cpp(2.03 KB)
📄 MCMachOStreamer.cpp(18.55 KB)
📄 MCMachObjectTargetWriter.cpp(780 B)
📄 MCNullStreamer.cpp(1.61 KB)
📄 MCObjectFileInfo.cpp(39.55 KB)
📄 MCObjectStreamer.cpp(28.26 KB)
📄 MCObjectWriter.cpp(1.82 KB)
📁 MCParser
📄 MCRegisterInfo.cpp(4.76 KB)
📄 MCSchedule.cpp(6.15 KB)
📄 MCSection.cpp(4.41 KB)
📄 MCSectionCOFF.cpp(3.52 KB)
📄 MCSectionELF.cpp(5.29 KB)
📄 MCSectionMachO.cpp(10.84 KB)
📄 MCSectionWasm.cpp(2.45 KB)
📄 MCSectionXCOFF.cpp(2.46 KB)
📄 MCStreamer.cpp(42.97 KB)
📄 MCSubtargetInfo.cpp(11.35 KB)
📄 MCSymbol.cpp(2.98 KB)
📄 MCSymbolELF.cpp(4.69 KB)
📄 MCSymbolXCOFF.cpp(1.73 KB)
📄 MCTargetOptions.cpp(990 B)
📄 MCTargetOptionsCommandFlags.cpp(4.42 KB)
📄 MCValue.cpp(1.42 KB)
📄 MCWasmObjectTargetWriter.cpp(727 B)
📄 MCWasmStreamer.cpp(7.59 KB)
📄 MCWin64EH.cpp(22.87 KB)
📄 MCWinCOFFStreamer.cpp(11.94 KB)
📄 MCWinEH.cpp(711 B)
📄 MCXCOFFObjectTargetWriter.cpp(596 B)
📄 MCXCOFFStreamer.cpp(4.87 KB)
📄 MachObjectWriter.cpp(37.79 KB)
📄 StringTableBuilder.cpp(5.26 KB)
📄 SubtargetFeature.cpp(2.6 KB)
📄 WasmObjectWriter.cpp(60.42 KB)
📄 WinCOFFObjectWriter.cpp(39.32 KB)
📄 XCOFFObjectWriter.cpp(31.62 KB)

Editing: MCSchedule.cpp

//===- MCSchedule.cpp - Scheduling ------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines the default scheduling model.
//
//===----------------------------------------------------------------------===//

#include "llvm/MC/MCSchedule.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <type_traits>

using namespace llvm;

static_assert(std::is_pod<MCSchedModel>::value,
              "We shouldn't have a static constructor here");
const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
                                            DefaultMicroOpBufferSize,
                                            DefaultLoopMicroOpBufferSize,
                                            DefaultLoadLatency,
                                            DefaultHighLatency,
                                            DefaultMispredictPenalty,
                                            false,
                                            true,
                                            0,
                                            nullptr,
                                            nullptr,
                                            0,
                                            0,
                                            nullptr,
                                            nullptr};

int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
                                      const MCSchedClassDesc &SCDesc) {
  int Latency = 0;
  for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries;
       DefIdx != DefEnd; ++DefIdx) {
    // Lookup the definition's write latency in SubtargetInfo.
    const MCWriteLatencyEntry *WLEntry =
        STI.getWriteLatencyEntry(&SCDesc, DefIdx);
    // Early exit if we found an invalid latency.
    if (WLEntry->Cycles < 0)
      return WLEntry->Cycles;
    Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles));
  }
  return Latency;
}

int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
                                      unsigned SchedClass) const {
  const MCSchedClassDesc &SCDesc = *getSchedClassDesc(SchedClass);
  if (!SCDesc.isValid())
    return 0;
  if (!SCDesc.isVariant())
    return MCSchedModel::computeInstrLatency(STI, SCDesc);

llvm_unreachable("unsupported variant scheduling class");
}

int MCSchedModel::computeInstrLatency(const MCSubtargetInfo &STI,
                                      const MCInstrInfo &MCII,
                                      const MCInst &Inst) const {
  unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
  const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);
  if (!SCDesc->isValid())
    return 0;

unsigned CPUID = getProcessorID();
  while (SCDesc->isVariant()) {
    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
    SCDesc = getSchedClassDesc(SchedClass);
  }

if (SchedClass)
    return MCSchedModel::computeInstrLatency(STI, *SCDesc);

llvm_unreachable("unsupported variant scheduling class");
}

double
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
                                      const MCSchedClassDesc &SCDesc) {
  Optional<double> Throughput;
  const MCSchedModel &SM = STI.getSchedModel();
  const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
  const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
  for (; I != E; ++I) {
    if (!I->Cycles)
      continue;
    unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
    double Temp = NumUnits * 1.0 / I->Cycles;
    Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
  }
  if (Throughput.hasValue())
    return 1.0 / Throughput.getValue();

// If no throughput value was calculated, assume that we can execute at the
  // maximum issue width scaled by number of micro-ops for the schedule class.
  return ((double)SCDesc.NumMicroOps) / SM.IssueWidth;
}

double
MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
                                      const MCInstrInfo &MCII,
                                      const MCInst &Inst) const {
  unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
  const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass);

// If there's no valid class, assume that the instruction executes/completes
  // at the maximum issue width.
  if (!SCDesc->isValid())
    return 1.0 / IssueWidth;

unsigned CPUID = getProcessorID();
  while (SCDesc->isVariant()) {
    SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID);
    SCDesc = getSchedClassDesc(SchedClass);
  }

if (SchedClass)
    return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);

llvm_unreachable("unsupported variant scheduling class");
}

double
MCSchedModel::getReciprocalThroughput(unsigned SchedClass,
                                      const InstrItineraryData &IID) {
  Optional<double> Throughput;
  const InstrStage *I = IID.beginStage(SchedClass);
  const InstrStage *E = IID.endStage(SchedClass);
  for (; I != E; ++I) {
    if (!I->getCycles())
      continue;
    double Temp = countPopulation(I->getUnits()) * 1.0 / I->getCycles();
    Throughput = Throughput ? std::min(Throughput.getValue(), Temp) : Temp;
  }
  if (Throughput.hasValue())
    return 1.0 / Throughput.getValue();

// If there are no execution resources specified for this class, then assume
  // that it can execute at the maximum default issue width.
  return 1.0 / DefaultIssueWidth;
}

unsigned
MCSchedModel::getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
                                       unsigned WriteResourceID) {
  if (Entries.empty())
    return 0;

int DelayCycles = 0;
  for (const MCReadAdvanceEntry &E : Entries) {
    if (E.WriteResourceID != WriteResourceID)
      continue;
    DelayCycles = std::min(DelayCycles, E.Cycles);
  }

return std::abs(DelayCycles);
}

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Editing: MCSchedule.cpp

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