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📄 ConstantPools.h(3.35 KB)
📄 LaneBitmask.h(3.24 KB)
📄 MCAsmBackend.h(8.09 KB)
📄 MCAsmInfo.h(25.48 KB)
📄 MCAsmInfoCOFF.h(900 B)
📄 MCAsmInfoDarwin.h(927 B)
📄 MCAsmInfoELF.h(711 B)
📄 MCAsmInfoWasm.h(612 B)
📄 MCAsmInfoXCOFF.h(792 B)
📄 MCAsmLayout.h(3.75 KB)
📄 MCAsmMacro.h(4.54 KB)
📄 MCAssembler.h(16.1 KB)
📄 MCCodeEmitter.h(1.53 KB)
📄 MCCodeView.h(9.03 KB)
📄 MCContext.h(31.99 KB)
📄 MCDirectives.h(3.12 KB)
📁 MCDisassembler
📄 MCDwarf.h(21.46 KB)
📄 MCELFObjectWriter.h(5.27 KB)
📄 MCELFStreamer.h(3.97 KB)
📄 MCExpr.h(21.55 KB)
📄 MCFixedLenDisassembler.h(1.39 KB)
📄 MCFixup.h(7.4 KB)
📄 MCFixupKindInfo.h(1.6 KB)
📄 MCFragment.h(17.72 KB)
📄 MCInst.h(6.06 KB)
📄 MCInstBuilder.h(1.76 KB)
📄 MCInstPrinter.h(5.88 KB)
📄 MCInstrAnalysis.h(6.8 KB)
📄 MCInstrDesc.h(25.13 KB)
📄 MCInstrInfo.h(2.93 KB)
📄 MCInstrItineraries.h(9.02 KB)
📄 MCLabel.h(1.63 KB)
📄 MCLinkerOptimizationHint.h(5.73 KB)
📄 MCMachObjectWriter.h(9.77 KB)
📄 MCObjectFileInfo.h(16.57 KB)
📄 MCObjectStreamer.h(8.78 KB)
📄 MCObjectWriter.h(4.44 KB)
📁 MCParser
📄 MCRegister.h(4.16 KB)
📄 MCRegisterInfo.h(28.96 KB)
📄 MCSchedule.h(16.25 KB)
📄 MCSection.h(6.52 KB)
📄 MCSectionCOFF.h(3.37 KB)
📄 MCSectionELF.h(3.3 KB)
📄 MCSectionMachO.h(3.15 KB)
📄 MCSectionWasm.h(2.78 KB)
📄 MCSectionXCOFF.h(3.22 KB)
📄 MCStreamer.h(43.55 KB)
📄 MCSubtargetInfo.h(10.04 KB)
📄 MCSymbol.h(13.8 KB)
📄 MCSymbolCOFF.h(1.62 KB)
📄 MCSymbolELF.h(1.45 KB)
📄 MCSymbolMachO.h(4.18 KB)
📄 MCSymbolWasm.h(4.28 KB)
📄 MCSymbolXCOFF.h(2.39 KB)
📄 MCTargetOptions.h(2.29 KB)
📄 MCTargetOptionsCommandFlags.h(1.26 KB)
📄 MCValue.h(2.42 KB)
📄 MCWasmObjectWriter.h(1.61 KB)
📄 MCWasmStreamer.h(2.83 KB)
📄 MCWin64EH.h(2.41 KB)
📄 MCWinCOFFObjectWriter.h(1.81 KB)
📄 MCWinCOFFStreamer.h(3.05 KB)
📄 MCWinEH.h(1.97 KB)
📄 MCXCOFFObjectWriter.h(1.45 KB)
📄 MCXCOFFStreamer.h(1.86 KB)
📄 MachineLocation.h(2.04 KB)
📄 SectionKind.h(7.53 KB)
📄 StringTableBuilder.h(2.47 KB)
📄 SubtargetFeature.h(7.12 KB)

Editing: MCSubtargetInfo.h

//===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the subtarget options of a Target machine.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_MC_MCSUBTARGETINFO_H
#define LLVM_MC_MCSUBTARGETINFO_H

#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/MC/SubtargetFeature.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <string>

namespace llvm {

class MCInst;

//===----------------------------------------------------------------------===//

/// Used to provide key value pairs for feature and CPU bit flags.
struct SubtargetFeatureKV {
  const char *Key;                      ///< K-V key string
  const char *Desc;                     ///< Help descriptor
  unsigned Value;                       ///< K-V integer value
  FeatureBitArray Implies;              ///< K-V bit mask

/// Compare routine for std::lower_bound
  bool operator<(StringRef S) const {
    return StringRef(Key) < S;
  }

/// Compare routine for std::is_sorted.
  bool operator<(const SubtargetFeatureKV &Other) const {
    return StringRef(Key) < StringRef(Other.Key);
  }
};

//===----------------------------------------------------------------------===//

/// Used to provide key value pairs for feature and CPU bit flags.
struct SubtargetSubTypeKV {
  const char *Key;                      ///< K-V key string
  FeatureBitArray Implies;              ///< K-V bit mask
  const MCSchedModel *SchedModel;

/// Compare routine for std::lower_bound
  bool operator<(StringRef S) const {
    return StringRef(Key) < S;
  }

/// Compare routine for std::is_sorted.
  bool operator<(const SubtargetSubTypeKV &Other) const {
    return StringRef(Key) < StringRef(Other.Key);
  }
};

//===----------------------------------------------------------------------===//
///
/// Generic base class for all target subtargets.
///
class MCSubtargetInfo {
  Triple TargetTriple;
  std::string CPU; // CPU being targeted.
  ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
  ArrayRef<SubtargetSubTypeKV> ProcDesc;  // Processor descriptions

// Scheduler machine model
  const MCWriteProcResEntry *WriteProcResTable;
  const MCWriteLatencyEntry *WriteLatencyTable;
  const MCReadAdvanceEntry *ReadAdvanceTable;
  const MCSchedModel *CPUSchedModel;

const InstrStage *Stages;            // Instruction itinerary stages
  const unsigned *OperandCycles;       // Itinerary operand cycles
  const unsigned *ForwardingPaths;
  FeatureBitset FeatureBits;           // Feature bits for current CPU + FS

public:
  MCSubtargetInfo(const MCSubtargetInfo &) = default;
  MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                  ArrayRef<SubtargetFeatureKV> PF,
                  ArrayRef<SubtargetSubTypeKV> PD,
                  const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                  const MCReadAdvanceEntry *RA, const InstrStage *IS,
                  const unsigned *OC, const unsigned *FP);
  MCSubtargetInfo() = delete;
  MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
  MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
  virtual ~MCSubtargetInfo() = default;

const Triple &getTargetTriple() const { return TargetTriple; }
  StringRef getCPU() const { return CPU; }

const FeatureBitset& getFeatureBits() const { return FeatureBits; }
  void setFeatureBits(const FeatureBitset &FeatureBits_) {
    FeatureBits = FeatureBits_;
  }

bool hasFeature(unsigned Feature) const {
    return FeatureBits[Feature];
  }

protected:
  /// Initialize the scheduling model and feature bits.
  ///
  /// FIXME: Find a way to stick this in the constructor, since it should only
  /// be called during initialization.
  void InitMCProcessorInfo(StringRef CPU, StringRef FS);

public:
  /// Set the features to the default for the given CPU with an appended feature
  /// string.
  void setDefaultFeatures(StringRef CPU, StringRef FS);

/// Toggle a feature and return the re-computed feature bits.
  /// This version does not change the implied bits.
  FeatureBitset ToggleFeature(uint64_t FB);

/// Toggle a feature and return the re-computed feature bits.
  /// This version does not change the implied bits.
  FeatureBitset ToggleFeature(const FeatureBitset& FB);

/// Toggle a set of features and return the re-computed feature bits.
  /// This version will also change all implied bits.
  FeatureBitset ToggleFeature(StringRef FS);

/// Apply a feature flag and return the re-computed feature bits, including
  /// all feature bits implied by the flag.
  FeatureBitset ApplyFeatureFlag(StringRef FS);

/// Set/clear additional feature bits, including all other bits they imply.
  FeatureBitset SetFeatureBitsTransitively(const FeatureBitset& FB);
  FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB);

/// Check whether the subtarget features are enabled/disabled as per
  /// the provided string, ignoring all other features.
  bool checkFeatures(StringRef FS) const;

/// Get the machine model of a CPU.
  const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;

/// Get the machine model for this subtarget's CPU.
  const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }

/// Return an iterator at the first process resource consumed by the given
  /// scheduling class.
  const MCWriteProcResEntry *getWriteProcResBegin(
    const MCSchedClassDesc *SC) const {
    return &WriteProcResTable[SC->WriteProcResIdx];
  }
  const MCWriteProcResEntry *getWriteProcResEnd(
    const MCSchedClassDesc *SC) const {
    return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
  }

const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
                                                  unsigned DefIdx) const {
    assert(DefIdx < SC->NumWriteLatencyEntries &&
           "MachineModel does not specify a WriteResource for DefIdx");

return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
  }

int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
                           unsigned WriteResID) const {
    // TODO: The number of read advance entries in a class can be significant
    // (~50). Consider compressing the WriteID into a dense ID of those that are
    // used by ReadAdvance and representing them as a bitset.
    for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
           *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
      if (I->UseIdx < UseIdx)
        continue;
      if (I->UseIdx > UseIdx)
        break;
      // Find the first WriteResIdx match, which has the highest cycle count.
      if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
        return I->Cycles;
      }
    }
    return 0;
  }

/// Return the set of ReadAdvance entries declared by the scheduling class
  /// descriptor in input.
  ArrayRef<MCReadAdvanceEntry>
  getReadAdvanceEntries(const MCSchedClassDesc &SC) const {
    if (!SC.NumReadAdvanceEntries)
      return ArrayRef<MCReadAdvanceEntry>();
    return ArrayRef<MCReadAdvanceEntry>(&ReadAdvanceTable[SC.ReadAdvanceIdx],
                                        SC.NumReadAdvanceEntries);
  }

/// Get scheduling itinerary of a CPU.
  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;

/// Initialize an InstrItineraryData instance.
  void initInstrItins(InstrItineraryData &InstrItins) const;

/// Resolve a variant scheduling class for the given MCInst and CPU.
  virtual unsigned
  resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
                           unsigned CPUID) const {
    return 0;
  }

/// Check whether the CPU string is valid.
  bool isCPUStringValid(StringRef CPU) const {
    auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU);
    return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
  }

virtual unsigned getHwMode() const { return 0; }

/// Return the cache size in bytes for the given level of cache.
  /// Level is zero-based, so a value of zero means the first level of
  /// cache.
  ///
  virtual Optional<unsigned> getCacheSize(unsigned Level) const;

/// Return the cache associatvity for the given level of cache.
  /// Level is zero-based, so a value of zero means the first level of
  /// cache.
  ///
  virtual Optional<unsigned> getCacheAssociativity(unsigned Level) const;

/// Return the target cache line size in bytes at a given level.
  ///
  virtual Optional<unsigned> getCacheLineSize(unsigned Level) const;

/// Return the target cache line size in bytes.  By default, return
  /// the line size for the bottom-most level of cache.  This provides
  /// a more convenient interface for the common case where all cache
  /// levels have the same line size.  Return zero if there is no
  /// cache model.
  ///
  virtual unsigned getCacheLineSize() const {
    Optional<unsigned> Size = getCacheLineSize(0);
    if (Size)
      return *Size;

return 0;
  }

/// Return the preferred prefetch distance in terms of instructions.
  ///
  virtual unsigned getPrefetchDistance() const;

/// Return the maximum prefetch distance in terms of loop
  /// iterations.
  ///
  virtual unsigned getMaxPrefetchIterationsAhead() const;

/// \return True if prefetching should also be done for writes.
  ///
  virtual bool enableWritePrefetching() const;

/// Return the minimum stride necessary to trigger software
  /// prefetching.
  ///
  virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
                                        unsigned NumStridedMemAccesses,
                                        unsigned NumPrefetches,
                                        bool HasCall) const;
};

} // end namespace llvm

#endif // LLVM_MC_MCSUBTARGETINFO_H

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Editing: MCSubtargetInfo.h

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