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usr / src / contrib / llvm-project / llvm / lib / Target / Mips /

📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 MSA.txt(3.64 KB)
📄 MicroMips32r6InstrFormats.td(20.42 KB)
📄 MicroMips32r6InstrInfo.td(86.7 KB)
📄 MicroMipsDSPInstrFormats.td(6.55 KB)
📄 MicroMipsDSPInstrInfo.td(33.92 KB)
📄 MicroMipsInstrFPU.td(20.28 KB)
📄 MicroMipsInstrFormats.td(19.75 KB)
📄 MicroMipsInstrInfo.td(63.12 KB)
📄 MicroMipsSizeReduction.cpp(26.44 KB)
📄 Mips.h(1.85 KB)
📄 Mips.td(13.99 KB)
📄 Mips16FrameLowering.cpp(6.34 KB)
📄 Mips16FrameLowering.h(1.73 KB)
📄 Mips16HardFloat.cpp(15.87 KB)
📄 Mips16HardFloatInfo.cpp(1.45 KB)
📄 Mips16HardFloatInfo.h(1.33 KB)
📄 Mips16ISelDAGToDAG.cpp(7.33 KB)
📄 Mips16ISelDAGToDAG.h(1.8 KB)
📄 Mips16ISelLowering.cpp(29.05 KB)
📄 Mips16ISelLowering.h(3.29 KB)
📄 Mips16InstrFormats.td(16.29 KB)
📄 Mips16InstrInfo.cpp(17.93 KB)
📄 Mips16InstrInfo.h(5.33 KB)
📄 Mips16InstrInfo.td(51.26 KB)
📄 Mips16RegisterInfo.cpp(4.81 KB)
📄 Mips16RegisterInfo.h(1.56 KB)
📄 Mips32r6InstrFormats.td(14.85 KB)
📄 Mips32r6InstrInfo.td(47.55 KB)
📄 Mips64InstrInfo.td(58.62 KB)
📄 Mips64r6InstrInfo.td(15.93 KB)
📄 MipsAnalyzeImmediate.cpp(4.62 KB)
📄 MipsAnalyzeImmediate.h(2.24 KB)
📄 MipsAsmPrinter.cpp(43.89 KB)
📄 MipsAsmPrinter.h(6.04 KB)
📄 MipsBranchExpansion.cpp(29.72 KB)
📄 MipsCCState.cpp(6.71 KB)
📄 MipsCCState.h(6.14 KB)
📄 MipsCallLowering.cpp(23.62 KB)
📄 MipsCallLowering.h(3.35 KB)
📄 MipsCallingConv.td(17.55 KB)
📄 MipsCondMov.td(14.56 KB)
📄 MipsConstantIslandPass.cpp(62.17 KB)
📄 MipsDSPInstrFormats.td(7.39 KB)
📄 MipsDSPInstrInfo.td(68.68 KB)
📄 MipsDelaySlotFiller.cpp(32.55 KB)
📄 MipsEVAInstrFormats.td(2.51 KB)
📄 MipsEVAInstrInfo.td(8.52 KB)
📄 MipsExpandPseudo.cpp(30.1 KB)
📄 MipsFastISel.cpp(66.8 KB)
📄 MipsFrameLowering.cpp(5.75 KB)
📄 MipsFrameLowering.h(1.74 KB)
📄 MipsISelDAGToDAG.cpp(10.22 KB)
📄 MipsISelDAGToDAG.h(6.13 KB)
📄 MipsISelLowering.cpp(192.31 KB)
📄 MipsISelLowering.h(27.02 KB)
📄 MipsInstrFPU.td(44.82 KB)
📄 MipsInstrFormats.td(19.73 KB)
📄 MipsInstrInfo.cpp(28.1 KB)
📄 MipsInstrInfo.h(7.87 KB)
📄 MipsInstrInfo.td(138.02 KB)
📄 MipsInstructionSelector.cpp(34.44 KB)
📄 MipsLegalizerInfo.cpp(21.07 KB)
📄 MipsLegalizerInfo.h(1.19 KB)
📄 MipsMCInstLower.cpp(9.68 KB)
📄 MipsMCInstLower.h(1.77 KB)
📄 MipsMSAInstrFormats.td(9.18 KB)
📄 MipsMSAInstrInfo.td(182.92 KB)
📄 MipsMTInstrFormats.td(2.44 KB)
📄 MipsMTInstrInfo.td(7.59 KB)
📄 MipsMachineFunction.cpp(7.22 KB)
📄 MipsMachineFunction.h(4.37 KB)
📄 MipsModuleISelDAGToDAG.cpp(1.67 KB)
📄 MipsOptimizePICCall.cpp(9.78 KB)
📄 MipsOptionRecord.h(2.9 KB)
📄 MipsOs16.cpp(4.18 KB)
📄 MipsPfmCounters.td(706 B)
📄 MipsPreLegalizerCombiner.cpp(3.93 KB)
📄 MipsRegisterBankInfo.cpp(26.01 KB)
📄 MipsRegisterBankInfo.h(9.13 KB)
📄 MipsRegisterBanks.td(573 B)
📄 MipsRegisterInfo.cpp(10.41 KB)
📄 MipsRegisterInfo.h(2.82 KB)
📄 MipsRegisterInfo.td(23.18 KB)
📄 MipsSEFrameLowering.cpp(34.47 KB)
📄 MipsSEFrameLowering.h(1.88 KB)
📄 MipsSEISelDAGToDAG.cpp(49.41 KB)
📄 MipsSEISelDAGToDAG.h(5.92 KB)
📄 MipsSEISelLowering.cpp(140.76 KB)
📄 MipsSEISelLowering.h(6.25 KB)
📄 MipsSEInstrInfo.cpp(34.71 KB)
📄 MipsSEInstrInfo.h(5.34 KB)
📄 MipsSERegisterInfo.cpp(8.44 KB)
📄 MipsSERegisterInfo.h(1.2 KB)
📄 MipsSchedule.td(38.24 KB)
📄 MipsScheduleGeneric.td(71.71 KB)
📄 MipsScheduleP5600.td(27.85 KB)
📄 MipsSubtarget.cpp(10.72 KB)
📄 MipsSubtarget.h(13.43 KB)
📄 MipsTargetMachine.cpp(12.66 KB)
📄 MipsTargetMachine.h(3.08 KB)
📄 MipsTargetObjectFile.cpp(7.39 KB)
📄 MipsTargetObjectFile.h(2.02 KB)
📄 MipsTargetStreamer.h(14.58 KB)
📄 Relocation.txt(3.91 KB)
📁 TargetInfo

Editing: MipsDSPInstrFormats.td

//===- MipsDSPInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

class DspMMRel;

def Dsp2MicroMips : InstrMapping {
  let FilterClass = "DspMMRel";
  // Instructions with the same BaseOpcode and isNVStore values form a row.
  let RowFields = ["BaseOpcode"];
  // Instructions with the same predicate sense form a column.
  let ColFields = ["Arch"];
  // The key column is the unpredicated instructions.
  let KeyCol = ["dsp"];
  // Value columns are PredSense=true and PredSense=false
  let ValueCols = [["dsp"], ["mmdsp"]];
}

def HasDSP : Predicate<"Subtarget->hasDSP()">,
             AssemblerPredicate<(all_of FeatureDSP)>;
def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">,
               AssemblerPredicate<(all_of FeatureDSPR2)>;
def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">,
               AssemblerPredicate<(all_of FeatureDSPR3)>;

class ISA_DSPR2 {
  list<Predicate> ASEPredicate = [HasDSPR2];
}

class ISA_DSPR3 {
  list<Predicate> ASEPredicate = [HasDSPR3];
}

// Fields.
class Field6<bits<6> val> {
  bits<6> V = val;
}

def SPECIAL3_OPCODE : Field6<0b011111>;
def REGIMM_OPCODE : Field6<0b000001>;

class DSPInst<string opstr = "">
    : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
  let ASEPredicate = [HasDSP];
  string BaseOpcode = opstr;
  string Arch = "dsp";
}

class PseudoDSP<dag outs, dag ins, list<dag> pattern,
                InstrItinClass itin = IIPseudo>
    : MipsPseudo<outs, ins, pattern, itin> {
  let ASEPredicate = [HasDSP];
}

class DSPInstAlias<string Asm, dag Result, bit Emit = 0b1>
    : InstAlias<Asm, Result, Emit>, PredicateControl {
  let ASEPredicate = [HasDSP];
}

// ADDU.QB sub-class format.
class ADDU_QB_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<5> rs;
  bits<5> rt;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010000;
}

class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<5> rs;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = 0;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010000;
}

// CMPU.EQ.QB sub-class format.
class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
  bits<5> rs;
  bits<5> rt;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = 0;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010001;
}

class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
  bits<5> rs;
  bits<5> rt;
  bits<5> rd;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010001;
}

class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
  bits<5> rs;
  bits<5> rt;
  bits<5> sa;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = sa;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010001;
}

// ABSQ_S.PH sub-class format.
class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<5> rt;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = 0;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010010;
}

class REPL_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<10> imm;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-16} = imm;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010010;
}

// SHLL.QB sub-class format.
class SHLL_QB_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<5> rt;
  bits<5> rs_sa;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs_sa;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0}   = 0b010011;
}

// LX sub-class format.
class LX_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<5> base;
  bits<5> index;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = base;
  let Inst{20-16} = index;
  let Inst{15-11} = rd;
  let Inst{10-6}  = op;
  let Inst{5-0} = 0b001010;
}

// ADDUH.QB sub-class format.
class ADDUH_QB_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<5> rs;
  bits<5> rt;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b011000;
}

// APPEND sub-class format.
class APPEND_FMT<bits<5> op> : DSPInst {
  bits<5> rt;
  bits<5> rs;
  bits<5> sa;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = sa;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b110001;
}

// DPA.W.PH sub-class format.
class DPA_W_PH_FMT<bits<5> op> : DSPInst {
  bits<2> ac;
  bits<5> rs;
  bits<5> rt;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-13} = 0;
  let Inst{12-11} = ac;
  let Inst{10-6}  = op;
  let Inst{5-0} = 0b110000;
}

// MULT sub-class format.
class MULT_FMT<bits<6> opcode, bits<6> funct> : DSPInst {
  bits<2> ac;
  bits<5> rs;
  bits<5> rt;

let Opcode = opcode;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-13} = 0;
  let Inst{12-11} = ac;
  let Inst{10-6}  = 0;
  let Inst{5-0} = funct;
}

// MFHI sub-class format.
class MFHI_FMT<bits<6> funct> : DSPInst {
  bits<5> rd;
  bits<2> ac;

let Inst{31-26} = 0;
  let Inst{25-23} = 0;
  let Inst{22-21} = ac;
  let Inst{20-16} = 0;
  let Inst{15-11} = rd;
  let Inst{10-6} = 0;
  let Inst{5-0} = funct;
}

// MTHI sub-class format.
class MTHI_FMT<bits<6> funct> : DSPInst {
  bits<5> rs;
  bits<2> ac;

let Inst{31-26} = 0;
  let Inst{25-21} = rs;
  let Inst{20-13} = 0;
  let Inst{12-11} = ac;
  let Inst{10-6} = 0;
  let Inst{5-0} = funct;
}

// EXTR.W sub-class format (type 1).
class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
  bits<5> rt;
  bits<2> ac;
  bits<5> shift_rs;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = shift_rs;
  let Inst{20-16} = rt;
  let Inst{15-13} = 0;
  let Inst{12-11} = ac;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b111000;
}

// SHILO sub-class format.
class SHILO_R1_FMT<bits<5> op> : DSPInst {
  bits<2> ac;
  bits<6> shift;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-20} = shift;
  let Inst{19-13} = 0;
  let Inst{12-11} = ac;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b111000;
}

class SHILO_R2_FMT<bits<5> op> : DSPInst {
  bits<2> ac;
  bits<5> rs;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-13} = 0;
  let Inst{12-11} = ac;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b111000;
}

class RDDSP_FMT<bits<5> op> : DSPInst {
  bits<5> rd;
  bits<10> mask;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-16} = mask;
  let Inst{15-11} = rd;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b111000;
}

class WRDSP_FMT<bits<5> op> : DSPInst {
  bits<5> rs;
  bits<10> mask;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-11} = mask;
  let Inst{10-6} = op;
  let Inst{5-0} = 0b111000;
}

class BPOSGE32_FMT<bits<5> op> : DSPInst {
  bits<16> offset;

let Opcode = REGIMM_OPCODE.V;

let Inst{25-21} = 0;
  let Inst{20-16} = op;
  let Inst{15-0} = offset;
}

// INSV sub-class format.
class INSV_FMT<bits<6> op> : DSPInst {
  bits<5> rt;
  bits<5> rs;

let Opcode = SPECIAL3_OPCODE.V;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-6} = 0;
  let Inst{5-0} = op;
}

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Editing: MipsDSPInstrFormats.td

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