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📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 MSA.txt(3.64 KB)
📄 MicroMips32r6InstrFormats.td(20.42 KB)
📄 MicroMips32r6InstrInfo.td(86.7 KB)
📄 MicroMipsDSPInstrFormats.td(6.55 KB)
📄 MicroMipsDSPInstrInfo.td(33.92 KB)
📄 MicroMipsInstrFPU.td(20.28 KB)
📄 MicroMipsInstrFormats.td(19.75 KB)
📄 MicroMipsInstrInfo.td(63.12 KB)
📄 MicroMipsSizeReduction.cpp(26.44 KB)
📄 Mips.h(1.85 KB)
📄 Mips.td(13.99 KB)
📄 Mips16FrameLowering.cpp(6.34 KB)
📄 Mips16FrameLowering.h(1.73 KB)
📄 Mips16HardFloat.cpp(15.87 KB)
📄 Mips16HardFloatInfo.cpp(1.45 KB)
📄 Mips16HardFloatInfo.h(1.33 KB)
📄 Mips16ISelDAGToDAG.cpp(7.33 KB)
📄 Mips16ISelDAGToDAG.h(1.8 KB)
📄 Mips16ISelLowering.cpp(29.05 KB)
📄 Mips16ISelLowering.h(3.29 KB)
📄 Mips16InstrFormats.td(16.29 KB)
📄 Mips16InstrInfo.cpp(17.93 KB)
📄 Mips16InstrInfo.h(5.33 KB)
📄 Mips16InstrInfo.td(51.26 KB)
📄 Mips16RegisterInfo.cpp(4.81 KB)
📄 Mips16RegisterInfo.h(1.56 KB)
📄 Mips32r6InstrFormats.td(14.85 KB)
📄 Mips32r6InstrInfo.td(47.55 KB)
📄 Mips64InstrInfo.td(58.62 KB)
📄 Mips64r6InstrInfo.td(15.93 KB)
📄 MipsAnalyzeImmediate.cpp(4.62 KB)
📄 MipsAnalyzeImmediate.h(2.24 KB)
📄 MipsAsmPrinter.cpp(43.89 KB)
📄 MipsAsmPrinter.h(6.04 KB)
📄 MipsBranchExpansion.cpp(29.72 KB)
📄 MipsCCState.cpp(6.71 KB)
📄 MipsCCState.h(6.14 KB)
📄 MipsCallLowering.cpp(23.62 KB)
📄 MipsCallLowering.h(3.35 KB)
📄 MipsCallingConv.td(17.55 KB)
📄 MipsCondMov.td(14.56 KB)
📄 MipsConstantIslandPass.cpp(62.17 KB)
📄 MipsDSPInstrFormats.td(7.39 KB)
📄 MipsDSPInstrInfo.td(68.68 KB)
📄 MipsDelaySlotFiller.cpp(32.55 KB)
📄 MipsEVAInstrFormats.td(2.51 KB)
📄 MipsEVAInstrInfo.td(8.52 KB)
📄 MipsExpandPseudo.cpp(30.1 KB)
📄 MipsFastISel.cpp(66.8 KB)
📄 MipsFrameLowering.cpp(5.75 KB)
📄 MipsFrameLowering.h(1.74 KB)
📄 MipsISelDAGToDAG.cpp(10.22 KB)
📄 MipsISelDAGToDAG.h(6.13 KB)
📄 MipsISelLowering.cpp(192.31 KB)
📄 MipsISelLowering.h(27.02 KB)
📄 MipsInstrFPU.td(44.82 KB)
📄 MipsInstrFormats.td(19.73 KB)
📄 MipsInstrInfo.cpp(28.1 KB)
📄 MipsInstrInfo.h(7.87 KB)
📄 MipsInstrInfo.td(138.02 KB)
📄 MipsInstructionSelector.cpp(34.44 KB)
📄 MipsLegalizerInfo.cpp(21.07 KB)
📄 MipsLegalizerInfo.h(1.19 KB)
📄 MipsMCInstLower.cpp(9.68 KB)
📄 MipsMCInstLower.h(1.77 KB)
📄 MipsMSAInstrFormats.td(9.18 KB)
📄 MipsMSAInstrInfo.td(182.92 KB)
📄 MipsMTInstrFormats.td(2.44 KB)
📄 MipsMTInstrInfo.td(7.59 KB)
📄 MipsMachineFunction.cpp(7.22 KB)
📄 MipsMachineFunction.h(4.37 KB)
📄 MipsModuleISelDAGToDAG.cpp(1.67 KB)
📄 MipsOptimizePICCall.cpp(9.78 KB)
📄 MipsOptionRecord.h(2.9 KB)
📄 MipsOs16.cpp(4.18 KB)
📄 MipsPfmCounters.td(706 B)
📄 MipsPreLegalizerCombiner.cpp(3.93 KB)
📄 MipsRegisterBankInfo.cpp(26.01 KB)
📄 MipsRegisterBankInfo.h(9.13 KB)
📄 MipsRegisterBanks.td(573 B)
📄 MipsRegisterInfo.cpp(10.41 KB)
📄 MipsRegisterInfo.h(2.82 KB)
📄 MipsRegisterInfo.td(23.18 KB)
📄 MipsSEFrameLowering.cpp(34.47 KB)
📄 MipsSEFrameLowering.h(1.88 KB)
📄 MipsSEISelDAGToDAG.cpp(49.41 KB)
📄 MipsSEISelDAGToDAG.h(5.92 KB)
📄 MipsSEISelLowering.cpp(140.76 KB)
📄 MipsSEISelLowering.h(6.25 KB)
📄 MipsSEInstrInfo.cpp(34.71 KB)
📄 MipsSEInstrInfo.h(5.34 KB)
📄 MipsSERegisterInfo.cpp(8.44 KB)
📄 MipsSERegisterInfo.h(1.2 KB)
📄 MipsSchedule.td(38.24 KB)
📄 MipsScheduleGeneric.td(71.71 KB)
📄 MipsScheduleP5600.td(27.85 KB)
📄 MipsSubtarget.cpp(10.72 KB)
📄 MipsSubtarget.h(13.43 KB)
📄 MipsTargetMachine.cpp(12.66 KB)
📄 MipsTargetMachine.h(3.08 KB)
📄 MipsTargetObjectFile.cpp(7.39 KB)
📄 MipsTargetObjectFile.h(2.02 KB)
📄 MipsTargetStreamer.h(14.58 KB)
📄 Relocation.txt(3.91 KB)
📁 TargetInfo

Editing: MipsMSAInstrFormats.td

//===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
                ASE_MSA {
  let EncodingPredicates = [HasStdEnc];
  let Inst{31-26} = 0b011110;
}

class MSACBranch : MSAInst {
  let Inst{31-26} = 0b010001;
}

class MSASpecial : MSAInst {
  let Inst{31-26} = 0b000000;
}

class MSAPseudo<dag outs, dag ins, list<dag> pattern,
                InstrItinClass itin = IIPseudo>:
  MipsPseudo<outs, ins, pattern, itin> {
  let EncodingPredicates = [HasStdEnc];
  let ASEPredicate = [HasMSA];
}

class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;
  bits<3> m;

let Inst{25-23} = major;
  let Inst{22-19} = 0b1110;
  let Inst{18-16} = m;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;
  bits<4> m;

let Inst{25-23} = major;
  let Inst{22-20} = 0b110;
  let Inst{19-16} = m;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;
  bits<5> m;

let Inst{25-23} = major;
  let Inst{22-21} = 0b10;
  let Inst{20-16} = m;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_BIT_D_FMT<bits<3> major, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;
  bits<6> m;

let Inst{25-23} = major;
  let Inst{22} = 0b0;
  let Inst{21-16} = m;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<5> rs;
  bits<5> wd;

let Inst{25-18} = major;
  let Inst{17-16} = df;
  let Inst{15-11} = rs;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<5> rs;
  bits<5> wd;

let Inst{25-18} = major;
  let Inst{17-16} = df;
  let Inst{15-11} = rs;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;

let Inst{25-18} = major;
  let Inst{17-16} = df;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_2RF_FMT<bits<9> major, bits<1> df, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;

let Inst{25-17} = major;
  let Inst{16} = df;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_3R_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<5> wt;
  bits<5> ws;
  bits<5> wd;

let Inst{25-23} = major;
  let Inst{22-21} = df;
  let Inst{20-16} = wt;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
  bits<5> wt;
  bits<5> ws;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21} = df;
  let Inst{20-16} = wt;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<5> rt;
  bits<5> ws;
  bits<5> wd;

let Inst{25-23} = major;
  let Inst{22-21} = df;
  let Inst{20-16} = rt;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
  bits<5> ws;
  bits<5> wd;

let Inst{25-16} = major;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_CFCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
  bits<5> rd;
  bits<5> cs;

let Inst{25-16} = major;
  let Inst{15-11} = cs;
  let Inst{10-6} = rd;
  let Inst{5-0} = minor;
}

class MSA_ELM_CTCMSA_FMT<bits<10> major, bits<6> minor>: MSAInst {
  bits<5> rs;
  bits<5> cd;

let Inst{25-16} = major;
  let Inst{15-11} = rs;
  let Inst{10-6} = cd;
  let Inst{5-0} = minor;
}

class MSA_ELM_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-20} = 0b00;
  let Inst{19-16} = n{3-0};
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-19} = 0b100;
  let Inst{18-16} = n{2-0};
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-18} = 0b1100;
  let Inst{17-16} = n{1-0};
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-17} = 0b11100;
  let Inst{16} = n{0};
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_COPY_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> rd;

let Inst{25-22} = major;
  let Inst{21-20} = 0b00;
  let Inst{19-16} = n{3-0};
  let Inst{15-11} = ws;
  let Inst{10-6} = rd;
  let Inst{5-0} = minor;
}

class MSA_ELM_COPY_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> rd;

let Inst{25-22} = major;
  let Inst{21-19} = 0b100;
  let Inst{18-16} = n{2-0};
  let Inst{15-11} = ws;
  let Inst{10-6} = rd;
  let Inst{5-0} = minor;
}

class MSA_ELM_COPY_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> rd;

let Inst{25-22} = major;
  let Inst{21-18} = 0b1100;
  let Inst{17-16} = n{1-0};
  let Inst{15-11} = ws;
  let Inst{10-6} = rd;
  let Inst{5-0} = minor;
}

class MSA_ELM_COPY_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<4> n;
  bits<5> ws;
  bits<5> rd;

let Inst{25-22} = major;
  let Inst{21-17} = 0b11100;
  let Inst{16} = n{0};
  let Inst{15-11} = ws;
  let Inst{10-6} = rd;
  let Inst{5-0} = minor;
}

class MSA_ELM_INSERT_B_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<6> n;
  bits<5> rs;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-20} = 0b00;
  let Inst{19-16} = n{3-0};
  let Inst{15-11} = rs;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_INSERT_H_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<6> n;
  bits<5> rs;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-19} = 0b100;
  let Inst{18-16} = n{2-0};
  let Inst{15-11} = rs;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_INSERT_W_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<6> n;
  bits<5> rs;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-18} = 0b1100;
  let Inst{17-16} = n{1-0};
  let Inst{15-11} = rs;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_ELM_INSERT_D_FMT<bits<4> major, bits<6> minor>: MSAInst {
  bits<6> n;
  bits<5> rs;
  bits<5> wd;

let Inst{25-22} = major;
  let Inst{21-17} = 0b11100;
  let Inst{16} = n{0};
  let Inst{15-11} = rs;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_I5_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<5> imm;
  bits<5> ws;
  bits<5> wd;

let Inst{25-23} = major;
  let Inst{22-21} = df;
  let Inst{20-16} = imm;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_I8_FMT<bits<2> major, bits<6> minor>: MSAInst {
  bits<8> u8;
  bits<5> ws;
  bits<5> wd;

let Inst{25-24} = major;
  let Inst{23-16} = u8;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
  bits<10> s10;
  bits<5> wd;

let Inst{25-23} = major;
  let Inst{22-21} = df;
  let Inst{20-11} = s10;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst {
  bits<21> addr;
  bits<5> wd;

let Inst{25-16} = addr{9-0};
  let Inst{15-11} = addr{20-16};
  let Inst{10-6} = wd;
  let Inst{5-2} = minor;
  let Inst{1-0} = df;
}

class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
  bits<5> wt;
  bits<5> ws;
  bits<5> wd;

let Inst{25-21} = major;
  let Inst{20-16} = wt;
  let Inst{15-11} = ws;
  let Inst{10-6} = wd;
  let Inst{5-0} = minor;
}

class MSA_CBRANCH_FMT<bits<3> major, bits<2> df>: MSACBranch {
  bits<16> offset;
  bits<5> wt;

let Inst{25-23} = major;
  let Inst{22-21} = df;
  let Inst{20-16} = wt;
  let Inst{15-0} = offset;
}

class MSA_CBRANCH_V_FMT<bits<5> major>: MSACBranch {
  bits<16> offset;
  bits<5> wt;

let Inst{25-21} = major;
  let Inst{20-16} = wt;
  let Inst{15-0} = offset;
}

class SPECIAL_LSA_FMT<bits<6> minor>: MSASpecial {
  bits<5> rs;
  bits<5> rt;
  bits<5> rd;
  bits<2> sa;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-8} = 0b000;
  let Inst{7-6} = sa;
  let Inst{5-0} = minor;
}

class SPECIAL_DLSA_FMT<bits<6> minor>: MSASpecial {
  bits<5> rs;
  bits<5> rt;
  bits<5> rd;
  bits<2> sa;

let Inst{25-21} = rs;
  let Inst{20-16} = rt;
  let Inst{15-11} = rd;
  let Inst{10-8} = 0b000;
  let Inst{7-6} = sa;
  let Inst{5-0} = minor;
}

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Editing: MipsMSAInstrFormats.td

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