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Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/NVPTX

usr / src / contrib / llvm-project / llvm / lib / Target / NVPTX /

📁 ..
📁 MCTargetDesc
📄 ManagedStringPool.h(1.41 KB)
📄 NVPTX.h(3.22 KB)
📄 NVPTX.td(4.99 KB)
📄 NVPTXAllocaHoisting.cpp(2.12 KB)
📄 NVPTXAllocaHoisting.h(755 B)
📄 NVPTXAsmPrinter.cpp(71.02 KB)
📄 NVPTXAsmPrinter.h(11.23 KB)
📄 NVPTXAssignValidGlobalNames.cpp(2.74 KB)
📄 NVPTXFrameLowering.cpp(3.41 KB)
📄 NVPTXFrameLowering.h(1.34 KB)
📄 NVPTXGenericToNVVM.cpp(11.59 KB)
📄 NVPTXISelDAGToDAG.cpp(134.03 KB)
📄 NVPTXISelDAGToDAG.h(3.54 KB)
📄 NVPTXISelLowering.cpp(198.59 KB)
📄 NVPTXISelLowering.h(15.65 KB)
📄 NVPTXImageOptimizer.cpp(5.64 KB)
📄 NVPTXInstrFormats.td(1.72 KB)
📄 NVPTXInstrInfo.cpp(7.88 KB)
📄 NVPTXInstrInfo.h(2.87 KB)
📄 NVPTXInstrInfo.td(133.35 KB)
📄 NVPTXIntrinsics.td(329.76 KB)
📄 NVPTXLowerAggrCopies.cpp(4.85 KB)
📄 NVPTXLowerAggrCopies.h(744 B)
📄 NVPTXLowerAlloca.cpp(4.27 KB)
📄 NVPTXLowerArgs.cpp(9.16 KB)
📄 NVPTXMCExpr.cpp(2.04 KB)
📄 NVPTXMCExpr.h(3.92 KB)
📄 NVPTXMachineFunctionInfo.h(1.71 KB)
📄 NVPTXPeephole.cpp(4.92 KB)
📄 NVPTXPrologEpilogPass.cpp(8.91 KB)
📄 NVPTXProxyRegErasure.cpp(3.81 KB)
📄 NVPTXRegisterInfo.cpp(4.41 KB)
📄 NVPTXRegisterInfo.h(2.04 KB)
📄 NVPTXRegisterInfo.td(3.12 KB)
📄 NVPTXReplaceImageHandles.cpp(6.27 KB)
📄 NVPTXSubtarget.cpp(2.15 KB)
📄 NVPTXSubtarget.h(3.02 KB)
📄 NVPTXTargetMachine.cpp(14.25 KB)
📄 NVPTXTargetMachine.h(3.33 KB)
📄 NVPTXTargetObjectFile.h(1.53 KB)
📄 NVPTXTargetTransformInfo.cpp(6.18 KB)
📄 NVPTXTargetTransformInfo.h(4.7 KB)
📄 NVPTXUtilities.cpp(9.37 KB)
📄 NVPTXUtilities.h(2.03 KB)
📄 NVVMIntrRange.cpp(4.88 KB)
📄 NVVMReflect.cpp(6.8 KB)
📁 TargetInfo
📄 cl_common_defines.h(3.94 KB)

Editing: NVPTXRegisterInfo.td

//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
//  Declarations that describe the PTX register file
//===----------------------------------------------------------------------===//

class NVPTXReg<string n> : Register<n> {
  let Namespace = "NVPTX";
}

class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
     : RegisterClass <"NVPTX", regTypes, alignment, regList>;

//===----------------------------------------------------------------------===//
//  Registers
//===----------------------------------------------------------------------===//

// Special Registers used as stack pointer
def VRFrame         : NVPTXReg<"%SP">;
def VRFrameLocal    : NVPTXReg<"%SPL">;

// Special Registers used as the stack
def VRDepot  : NVPTXReg<"%Depot">;

// We use virtual registers, but define a few physical registers here to keep
// SDAG and the MachineInstr layers happy.
foreach i = 0-4 in {
  def P#i  : NVPTXReg<"%p"#i>;  // Predicate
  def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
  def R#i  : NVPTXReg<"%r"#i>;  // 32-bit
  def RL#i : NVPTXReg<"%rd"#i>; // 64-bit
  def H#i  : NVPTXReg<"%h"#i>;  // 16-bit float
  def HH#i : NVPTXReg<"%hh"#i>; // 2x16-bit float
  def F#i  : NVPTXReg<"%f"#i>;  // 32-bit float
  def FL#i : NVPTXReg<"%fd"#i>; // 64-bit float

// Arguments
  def ia#i : NVPTXReg<"%ia"#i>;
  def la#i : NVPTXReg<"%la"#i>;
  def fa#i : NVPTXReg<"%fa"#i>;
  def da#i : NVPTXReg<"%da"#i>;
}

foreach i = 0-31 in {
  def ENVREG#i : NVPTXReg<"%envreg"#i>;
}

//===----------------------------------------------------------------------===//
//  Register classes
//===----------------------------------------------------------------------===//
def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;
def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>;
def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 4))>;
def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4))>;
def Float16Regs : NVPTXRegClass<[f16], 16, (add (sequence "H%u", 0, 4))>;
def Float16x2Regs : NVPTXRegClass<[v2f16], 32, (add (sequence "HH%u", 0, 4))>;
def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>;
def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>;
def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>;
def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 4))>;
def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 4))>;

// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRFrameLocal, VRDepot,
                                            (sequence "ENVREG%u", 0, 31))>;

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Editing: NVPTXRegisterInfo.td

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