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AArch64.cpp
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AArch64.h
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AMDGPU.cpp
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AMDGPU.h
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ARC.cpp
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ARC.h
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ARM.cpp
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ARM.h
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AVR.cpp
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AVR.h
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BPF.cpp
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BPF.h
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Hexagon.cpp
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Hexagon.h
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Lanai.cpp
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Lanai.h
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Le64.cpp
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Le64.h
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MSP430.cpp
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MSP430.h
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Mips.cpp
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Mips.h
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NVPTX.cpp
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NVPTX.h
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OSTargets.cpp
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OSTargets.h
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PNaCl.cpp
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PNaCl.h
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PPC.cpp
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PPC.h
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RISCV.cpp
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RISCV.h
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SPIR.cpp
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SPIR.h
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Sparc.cpp
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Sparc.h
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SystemZ.cpp
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SystemZ.h
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TCE.cpp
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TCE.h
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VE.cpp
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VE.h
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WebAssembly.cpp
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WebAssembly.h
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X86.cpp
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X86.h
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XCore.cpp
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XCore.h
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Editing: PNaCl.h
//===--- PNaCl.h - Declare PNaCl target feature support ---------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file declares PNaCl TargetInfo objects. // //===----------------------------------------------------------------------===// #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H #define LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H #include "Mips.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/ADT/Triple.h" #include "llvm/Support/Compiler.h" namespace clang { namespace targets { class LLVM_LIBRARY_VISIBILITY PNaClTargetInfo : public TargetInfo { public: PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple) { this->LongAlign = 32; this->LongWidth = 32; this->PointerAlign = 32; this->PointerWidth = 32; this->IntMaxType = TargetInfo::SignedLongLong; this->Int64Type = TargetInfo::SignedLongLong; this->DoubleAlign = 64; this->LongDoubleWidth = 64; this->LongDoubleAlign = 64; this->SizeType = TargetInfo::UnsignedInt; this->PtrDiffType = TargetInfo::SignedInt; this->IntPtrType = TargetInfo::SignedInt; this->RegParmMax = 0; // Disallow regparm } void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const; void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override { getArchDefines(Opts, Builder); } bool hasFeature(StringRef Feature) const override { return Feature == "pnacl"; } ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } BuiltinVaListKind getBuiltinVaListKind() const override { return TargetInfo::PNaClABIBuiltinVaList; } ArrayRef<const char *> getGCCRegNames() const override; ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override { return false; } const char *getClobbers() const override { return ""; } bool hasExtIntType() const override { return true; } }; // We attempt to use PNaCl (le32) frontend and Mips32EL backend. class LLVM_LIBRARY_VISIBILITY NaClMips32TargetInfo : public MipsTargetInfo { public: NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : MipsTargetInfo(Triple, Opts) {} BuiltinVaListKind getBuiltinVaListKind() const override { return TargetInfo::PNaClABIBuiltinVaList; } }; } // namespace targets } // namespace clang #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H
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