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📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 P9InstrResources.td(37.36 KB)
📄 PPC.h(4.69 KB)
📄 PPC.td(32.37 KB)
📄 PPCAsmPrinter.cpp(70.77 KB)
📄 PPCBoolRetToInt.cpp(9.97 KB)
📄 PPCBranchCoalescing.cpp(30.16 KB)
📄 PPCBranchSelector.cpp(15.97 KB)
📄 PPCCCState.cpp(1.08 KB)
📄 PPCCCState.h(1.19 KB)
📄 PPCCTRLoops.cpp(6.68 KB)
📄 PPCCallingConv.cpp(6.19 KB)
📄 PPCCallingConv.h(1.97 KB)
📄 PPCCallingConv.td(16.32 KB)
📄 PPCEarlyReturn.cpp(7.14 KB)
📄 PPCExpandISEL.cpp(17.93 KB)
📄 PPCFastISel.cpp(85.51 KB)
📄 PPCFrameLowering.cpp(98.6 KB)
📄 PPCFrameLowering.h(7.46 KB)
📄 PPCHazardRecognizers.cpp(14.02 KB)
📄 PPCHazardRecognizers.h(3.83 KB)
📄 PPCISelDAGToDAG.cpp(256.88 KB)
📄 PPCISelLowering.cpp(669.73 KB)
📄 PPCISelLowering.h(55.9 KB)
📄 PPCInstr64Bit.td(75.68 KB)
📄 PPCInstrAltivec.td(77.68 KB)
📄 PPCInstrBuilder.h(1.5 KB)
📄 PPCInstrFormats.td(57.38 KB)
📄 PPCInstrHTM.td(5.48 KB)
📄 PPCInstrInfo.cpp(171.06 KB)
📄 PPCInstrInfo.h(29.06 KB)
📄 PPCInstrInfo.td(233.39 KB)
📄 PPCInstrPrefix.td(41.72 KB)
📄 PPCInstrQPX.td(57.56 KB)
📄 PPCInstrSPE.td(49.71 KB)
📄 PPCInstrVSX.td(223.48 KB)
📄 PPCLoopInstrFormPrep.cpp(33.45 KB)
📄 PPCLowerMASSVEntries.cpp(6.42 KB)
📄 PPCMCInstLower.cpp(6.62 KB)
📄 PPCMIPeephole.cpp(63.48 KB)
📄 PPCMachineFunctionInfo.cpp(2.59 KB)
📄 PPCMachineFunctionInfo.h(9.15 KB)
📄 PPCMachineScheduler.cpp(4.03 KB)
📄 PPCMachineScheduler.h(1.81 KB)
📄 PPCMacroFusion.cpp(6.68 KB)
📄 PPCMacroFusion.def(1.8 KB)
📄 PPCMacroFusion.h(886 B)
📄 PPCPerfectShuffle.h(397.57 KB)
📄 PPCPfmCounters.td(705 B)
📄 PPCPreEmitPeephole.cpp(13.36 KB)
📄 PPCQPXLoadSplat.cpp(5.31 KB)
📄 PPCReduceCRLogicals.cpp(28.66 KB)
📄 PPCRegisterInfo.cpp(51.93 KB)
📄 PPCRegisterInfo.h(6.61 KB)
📄 PPCRegisterInfo.td(14.24 KB)
📄 PPCSchedule.td(5.21 KB)
📄 PPCSchedule440.td(34.57 KB)
📄 PPCScheduleA2.td(7.85 KB)
📄 PPCScheduleE500.td(16.59 KB)
📄 PPCScheduleE500mc.td(20.89 KB)
📄 PPCScheduleE5500.td(23.62 KB)
📄 PPCScheduleG3.td(4.49 KB)
📄 PPCScheduleG4.td(5.42 KB)
📄 PPCScheduleG4Plus.td(6.45 KB)
📄 PPCScheduleG5.td(7.1 KB)
📄 PPCScheduleP7.td(22.26 KB)
📄 PPCScheduleP8.td(23.96 KB)
📄 PPCScheduleP9.td(12.27 KB)
📄 PPCSubtarget.cpp(7.58 KB)
📄 PPCSubtarget.h(13.21 KB)
📄 PPCTLSDynamicCall.cpp(6.53 KB)
📄 PPCTOCRegDeps.cpp(5.3 KB)
📄 PPCTargetMachine.cpp(18.94 KB)
📄 PPCTargetMachine.h(2.2 KB)
📄 PPCTargetObjectFile.cpp(2.45 KB)
📄 PPCTargetObjectFile.h(1.19 KB)
📄 PPCTargetStreamer.h(1.02 KB)
📄 PPCTargetTransformInfo.cpp(38.72 KB)
📄 PPCTargetTransformInfo.h(5.6 KB)
📄 PPCVSXCopy.cpp(5.68 KB)
📄 PPCVSXFMAMutate.cpp(15.12 KB)
📄 PPCVSXSwapRemoval.cpp(36.78 KB)
📄 README_P9.txt(22.25 KB)
📁 TargetInfo

Editing: PPCFrameLowering.h

//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
#define LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H

#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/Target/TargetMachine.h"

namespace llvm {
class PPCSubtarget;

class PPCFrameLowering: public TargetFrameLowering {
  const PPCSubtarget &Subtarget;
  const unsigned ReturnSaveOffset;
  const unsigned TOCSaveOffset;
  const unsigned FramePointerSaveOffset;
  const unsigned LinkageSize;
  const unsigned BasePointerSaveOffset;
  const unsigned CRSaveOffset;

/**
   * Find register[s] that can be used in function prologue and epilogue
   *
   * Find register[s] that can be use as scratch register[s] in function
   * prologue and epilogue to save various registers (Link Register, Base
   * Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever
   * register[s] are available.
   *
   * This method will return true if it is able to find enough unique scratch
   * registers (1 or 2 depending on the requirement). If it is unable to find
   * enough available registers in the block, it will return false and set
   * any passed output parameter that corresponds to a required unique register
   * to PPC::NoRegister.
   *
   * \param[in] MBB The machine basic block to find an available register for
   * \param[in] UseAtEnd Specify whether the scratch register will be used at
   *                     the end of the basic block (i.e., will the scratch
   *                     register kill a register defined in the basic block)
   * \param[in] TwoUniqueRegsRequired Specify whether this basic block will
   *                                  require two unique scratch registers.
   * \param[out] SR1 The scratch register to use
   * \param[out] SR2 The second scratch register. If this pointer is not null
   *                 the function will attempt to set it to an available
   *                 register regardless of whether there is a hard requirement
   *                 for two unique scratch registers.
   * \return true if the required number of registers was found.
   *         false if the required number of scratch register weren't available.
   *         If either output parameter refers to a required scratch register
   *         that isn't available, it will be set to an invalid value.
   */
  bool findScratchRegister(MachineBasicBlock *MBB,
                           bool UseAtEnd,
                           bool TwoUniqueRegsRequired = false,
                           Register *SR1 = nullptr,
                           Register *SR2 = nullptr) const;
  bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;

/**
   * Create branch instruction for PPC::TCRETURN* (tail call return)
   *
   * \param[in] MBB that is terminated by PPC::TCRETURN*
   */
  void createTailCallBranchInstr(MachineBasicBlock &MBB) const;

/**
    * Check if the conditions are correct to allow for the stack update
    * to be moved past the CSR save/restore code.
    */
  bool stackUpdateCanBeMoved(MachineFunction &MF) const;

public:
  PPCFrameLowering(const PPCSubtarget &STI);

/**
   * Determine the frame layout and update the machine function.
   */
  unsigned determineFrameLayoutAndUpdate(MachineFunction &MF,
                                         bool UseEstimate = false) const;

/**
   * Determine the frame layout but do not update the machine function.
   * The MachineFunction object can be const in this case as it is not
   * modified.
   */
  unsigned determineFrameLayout(const MachineFunction &MF,
                                bool UseEstimate = false,
                                unsigned *NewMaxCallFrameSize = nullptr) const;

/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
  /// the function.
  void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
  void inlineStackProbe(MachineFunction &MF,
                        MachineBasicBlock &PrologMBB) const override;

bool hasFP(const MachineFunction &MF) const override;
  bool needsFP(const MachineFunction &MF) const;
  void replaceFPWithRealFP(MachineFunction &MF) const;

void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                            RegScavenger *RS = nullptr) const override;
  void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                     RegScavenger *RS = nullptr) const override;
  void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;

bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 ArrayRef<CalleeSavedInfo> CSI,
                                 const TargetRegisterInfo *TRI) const override;
  /// This function will assign callee saved gprs to volatile vector registers
  /// for prologue spills when applicable. It returns false if there are any
  /// registers which were not spilled to volatile vector registers.
  bool
  assignCalleeSavedSpillSlots(MachineFunction &MF,
                              const TargetRegisterInfo *TRI,
                              std::vector<CalleeSavedInfo> &CSI) const override;

MachineBasicBlock::iterator
  eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I) const override;

bool
  restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MI,
                              MutableArrayRef<CalleeSavedInfo> CSI,
                              const TargetRegisterInfo *TRI) const override;

/// targetHandlesStackFrameRounding - Returns true if the target is
  /// responsible for rounding up the stack frame (probably at emitPrologue
  /// time).
  bool targetHandlesStackFrameRounding() const override { return true; }

/// getReturnSaveOffset - Return the previous frame offset to save the
  /// return address.
  unsigned getReturnSaveOffset() const { return ReturnSaveOffset; }

/// getTOCSaveOffset - Return the previous frame offset to save the
  /// TOC register -- 64-bit SVR4 ABI only.
  unsigned getTOCSaveOffset() const;

/// getFramePointerSaveOffset - Return the previous frame offset to save the
  /// frame pointer.
  unsigned getFramePointerSaveOffset() const;

/// getBasePointerSaveOffset - Return the previous frame offset to save the
  /// base pointer.
  unsigned getBasePointerSaveOffset() const;

/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
  ///
  unsigned getLinkageSize() const { return LinkageSize; }

const SpillSlot *
  getCalleeSavedSpillSlots(unsigned &NumEntries) const override;

bool enableShrinkWrapping(const MachineFunction &MF) const override;

/// Methods used by shrink wrapping to determine if MBB can be used for the
  /// function prologue/epilogue.
  bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
  bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
};
} // End llvm namespace

#endif

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Editing: PPCFrameLowering.h

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