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AsmParser
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Disassembler
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MCTargetDesc
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P9InstrResources.td
(37.36 KB)
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PPC.h
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PPC.td
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PPCAsmPrinter.cpp
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PPCBoolRetToInt.cpp
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PPCBranchCoalescing.cpp
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PPCBranchSelector.cpp
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PPCCCState.cpp
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PPCCCState.h
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PPCCTRLoops.cpp
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PPCCallingConv.cpp
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PPCCallingConv.h
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PPCCallingConv.td
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PPCEarlyReturn.cpp
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PPCExpandISEL.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCFrameLowering.h
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PPCHazardRecognizers.cpp
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PPCHazardRecognizers.h
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCISelLowering.h
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PPCInstr64Bit.td
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PPCInstrAltivec.td
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PPCInstrBuilder.h
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PPCInstrFormats.td
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PPCInstrHTM.td
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PPCInstrInfo.cpp
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PPCInstrInfo.h
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PPCInstrInfo.td
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PPCInstrPrefix.td
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PPCInstrQPX.td
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PPCInstrSPE.td
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PPCInstrVSX.td
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PPCLoopInstrFormPrep.cpp
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PPCLowerMASSVEntries.cpp
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PPCMCInstLower.cpp
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PPCMIPeephole.cpp
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PPCMachineFunctionInfo.cpp
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PPCMachineFunctionInfo.h
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PPCMachineScheduler.cpp
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PPCMachineScheduler.h
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PPCMacroFusion.cpp
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PPCMacroFusion.def
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PPCMacroFusion.h
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PPCPerfectShuffle.h
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PPCPfmCounters.td
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PPCPreEmitPeephole.cpp
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PPCQPXLoadSplat.cpp
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PPCReduceCRLogicals.cpp
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PPCRegisterInfo.cpp
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PPCRegisterInfo.h
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PPCRegisterInfo.td
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PPCSchedule.td
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PPCSchedule440.td
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PPCScheduleA2.td
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PPCScheduleE500.td
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PPCScheduleE500mc.td
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PPCScheduleE5500.td
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PPCScheduleG3.td
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PPCScheduleG4.td
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PPCScheduleG4Plus.td
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PPCScheduleG5.td
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PPCScheduleP7.td
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PPCScheduleP8.td
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PPCScheduleP9.td
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PPCSubtarget.cpp
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PPCSubtarget.h
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PPCTLSDynamicCall.cpp
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PPCTOCRegDeps.cpp
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PPCTargetMachine.cpp
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PPCTargetMachine.h
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PPCTargetObjectFile.cpp
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PPCTargetObjectFile.h
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PPCTargetStreamer.h
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PPCTargetTransformInfo.cpp
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PPCTargetTransformInfo.h
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PPCVSXCopy.cpp
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PPCVSXFMAMutate.cpp
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PPCVSXSwapRemoval.cpp
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README_P9.txt
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TargetInfo
Editing: PPCHazardRecognizers.h
//===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines hazard recognizers for scheduling on PowerPC processors. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H #define LLVM_LIB_TARGET_POWERPC_PPCHAZARDRECOGNIZERS_H #include "PPCInstrInfo.h" #include "llvm/CodeGen/ScheduleHazardRecognizer.h" #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" #include "llvm/CodeGen/SelectionDAGNodes.h" namespace llvm { /// PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based /// hazard recognizer for PPC ooo processors with dispatch-group hazards. class PPCDispatchGroupSBHazardRecognizer : public ScoreboardHazardRecognizer { const ScheduleDAG *DAG; SmallVector<SUnit *, 7> CurGroup; unsigned CurSlots, CurBranches; bool isLoadAfterStore(SUnit *SU); bool isBCTRAfterSet(SUnit *SU); bool mustComeFirst(const MCInstrDesc *MCID, unsigned &NSlots); public: PPCDispatchGroupSBHazardRecognizer(const InstrItineraryData *ItinData, const ScheduleDAG *DAG_) : ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_), CurSlots(0), CurBranches(0) {} HazardType getHazardType(SUnit *SU, int Stalls) override; bool ShouldPreferAnother(SUnit* SU) override; unsigned PreEmitNoops(SUnit *SU) override; void EmitInstruction(SUnit *SU) override; void AdvanceCycle() override; void RecedeCycle() override; void Reset() override; void EmitNoop() override; }; /// PPCHazardRecognizer970 - This class defines a finite state automata that /// models the dispatch logic on the PowerPC 970 (aka G5) processor. This /// promotes good dispatch group formation and implements noop insertion to /// avoid structural hazards that cause significant performance penalties (e.g. /// setting the CTR register then branching through it within a dispatch group), /// or storing then loading from the same address within a dispatch group. class PPCHazardRecognizer970 : public ScheduleHazardRecognizer { const ScheduleDAG &DAG; unsigned NumIssued; // Number of insts issued, including advanced cycles. // Various things that can cause a structural hazard. // HasCTRSet - If the CTR register is set in this group, disallow BCTRL. bool HasCTRSet; // StoredPtr - Keep track of the address of any store. If we see a load from // the same address (or one that aliases it), disallow the store. We can have // up to four stores in one dispatch group, hence we track up to 4. // // This is null if we haven't seen a store yet. We keep track of both // operands of the store here, since we support [r+r] and [r+i] addressing. const Value *StoreValue[4]; int64_t StoreOffset[4]; uint64_t StoreSize[4]; unsigned NumStores; public: PPCHazardRecognizer970(const ScheduleDAG &DAG); HazardType getHazardType(SUnit *SU, int Stalls) override; void EmitInstruction(SUnit *SU) override; void AdvanceCycle() override; void Reset() override; private: /// EndDispatchGroup - Called when we are finishing a new dispatch group. /// void EndDispatchGroup(); /// GetInstrType - Classify the specified powerpc opcode according to its /// pipeline. PPCII::PPC970_Unit GetInstrType(unsigned Opcode, bool &isFirst, bool &isSingle,bool &isCracked, bool &isLoad, bool &isStore); bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset, const Value *LoadValue) const; }; } // end namespace llvm #endif
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