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AsmParser
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Disassembler
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MCTargetDesc
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P9InstrResources.td
(37.36 KB)
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PPC.h
(4.69 KB)
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PPC.td
(32.37 KB)
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PPCAsmPrinter.cpp
(70.77 KB)
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PPCBoolRetToInt.cpp
(9.97 KB)
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PPCBranchCoalescing.cpp
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PPCBranchSelector.cpp
(15.97 KB)
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PPCCCState.cpp
(1.08 KB)
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PPCCCState.h
(1.19 KB)
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PPCCTRLoops.cpp
(6.68 KB)
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PPCCallingConv.cpp
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PPCCallingConv.h
(1.97 KB)
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PPCCallingConv.td
(16.32 KB)
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PPCEarlyReturn.cpp
(7.14 KB)
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PPCExpandISEL.cpp
(17.93 KB)
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PPCFastISel.cpp
(85.51 KB)
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PPCFrameLowering.cpp
(98.6 KB)
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PPCFrameLowering.h
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PPCHazardRecognizers.cpp
(14.02 KB)
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PPCHazardRecognizers.h
(3.83 KB)
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PPCISelDAGToDAG.cpp
(256.88 KB)
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PPCISelLowering.cpp
(669.73 KB)
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PPCISelLowering.h
(55.9 KB)
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PPCInstr64Bit.td
(75.68 KB)
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PPCInstrAltivec.td
(77.68 KB)
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PPCInstrBuilder.h
(1.5 KB)
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PPCInstrFormats.td
(57.38 KB)
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PPCInstrHTM.td
(5.48 KB)
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PPCInstrInfo.cpp
(171.06 KB)
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PPCInstrInfo.h
(29.06 KB)
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PPCInstrInfo.td
(233.39 KB)
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PPCInstrPrefix.td
(41.72 KB)
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PPCInstrQPX.td
(57.56 KB)
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PPCInstrSPE.td
(49.71 KB)
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PPCInstrVSX.td
(223.48 KB)
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PPCLoopInstrFormPrep.cpp
(33.45 KB)
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PPCLowerMASSVEntries.cpp
(6.42 KB)
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PPCMCInstLower.cpp
(6.62 KB)
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PPCMIPeephole.cpp
(63.48 KB)
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PPCMachineFunctionInfo.cpp
(2.59 KB)
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PPCMachineFunctionInfo.h
(9.15 KB)
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PPCMachineScheduler.cpp
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PPCMachineScheduler.h
(1.81 KB)
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PPCMacroFusion.cpp
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PPCMacroFusion.def
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PPCMacroFusion.h
(886 B)
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PPCPerfectShuffle.h
(397.57 KB)
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PPCPfmCounters.td
(705 B)
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PPCPreEmitPeephole.cpp
(13.36 KB)
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PPCQPXLoadSplat.cpp
(5.31 KB)
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PPCReduceCRLogicals.cpp
(28.66 KB)
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PPCRegisterInfo.cpp
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PPCRegisterInfo.h
(6.61 KB)
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PPCRegisterInfo.td
(14.24 KB)
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PPCSchedule.td
(5.21 KB)
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PPCSchedule440.td
(34.57 KB)
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PPCScheduleA2.td
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PPCScheduleE500.td
(16.59 KB)
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PPCScheduleE500mc.td
(20.89 KB)
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PPCScheduleE5500.td
(23.62 KB)
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PPCScheduleG3.td
(4.49 KB)
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PPCScheduleG4.td
(5.42 KB)
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PPCScheduleG4Plus.td
(6.45 KB)
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PPCScheduleG5.td
(7.1 KB)
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PPCScheduleP7.td
(22.26 KB)
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PPCScheduleP8.td
(23.96 KB)
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PPCScheduleP9.td
(12.27 KB)
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PPCSubtarget.cpp
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PPCSubtarget.h
(13.21 KB)
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PPCTLSDynamicCall.cpp
(6.53 KB)
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PPCTOCRegDeps.cpp
(5.3 KB)
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PPCTargetMachine.cpp
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PPCTargetMachine.h
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PPCTargetObjectFile.cpp
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PPCTargetObjectFile.h
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PPCTargetStreamer.h
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PPCTargetTransformInfo.cpp
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PPCTargetTransformInfo.h
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PPCVSXCopy.cpp
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PPCVSXFMAMutate.cpp
(15.12 KB)
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PPCVSXSwapRemoval.cpp
(36.78 KB)
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README_P9.txt
(22.25 KB)
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TargetInfo
Editing: PPCInstrHTM.td
//===-- PPCInstrHTM.td - The PowerPC Hardware Transactional Memory -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file describes the Hardware Transactional Memory extension to the // PowerPC instruction set. // //===----------------------------------------------------------------------===// def HasHTM : Predicate<"Subtarget->hasHTM()">; def HTM_get_imm : SDNodeXForm<imm, [{ return getI32Imm (N->getZExtValue(), SDLoc(N)); }]>; let hasSideEffects = 1 in { def TCHECK_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins), "#TCHECK_RET", []>; def TBEGIN_RET : PPCCustomInserterPseudo<(outs gprc:$out), (ins u1imm:$R), "#TBEGIN_RET", []>; } let Predicates = [HasHTM] in { let Defs = [CR0] in { def TBEGIN : XForm_htm0 <31, 654, (outs), (ins u1imm:$R), "tbegin. $R", IIC_SprMTSPR, []>; def TEND : XForm_htm1 <31, 686, (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR, []>; def TABORT : XForm_base_r3xo <31, 910, (outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR, []>, isRecordForm { let RST = 0; let B = 0; } def TABORTWC : XForm_base_r3xo <31, 782, (outs), (ins u5imm:$RTS, gprc:$A, gprc:$B), "tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>, isRecordForm; def TABORTWCI : XForm_base_r3xo <31, 846, (outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B), "tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>, isRecordForm; def TABORTDC : XForm_base_r3xo <31, 814, (outs), (ins u5imm:$RTS, gprc:$A, gprc:$B), "tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>, isRecordForm; def TABORTDCI : XForm_base_r3xo <31, 878, (outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B), "tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>, isRecordForm; def TSR : XForm_htm2 <31, 750, (outs), (ins u1imm:$L), "tsr. $L", IIC_SprMTSPR, []>, isRecordForm; def TRECLAIM : XForm_base_r3xo <31, 942, (outs), (ins gprc:$A), "treclaim. $A", IIC_SprMTSPR, []>, isRecordForm { let RST = 0; let B = 0; } def TRECHKPT : XForm_base_r3xo <31, 1006, (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>, isRecordForm { let RST = 0; let A = 0; let B = 0; } } def TCHECK : XForm_htm3 <31, 718, (outs crrc:$BF), (ins), "tcheck $BF", IIC_SprMTSPR, []>; // Builtins // All HTM instructions, with the exception of tcheck, set CR0 with the // value of the MSR Transaction State (TS) bits that exist before the // instruction is executed. For tbegin., the EQ bit in CR0 can be used // to determine whether the transaction was successfully started (0) or // failed (1). We use an XORI pattern to 'flip' the bit to match the // tbegin builtin API which defines a return value of 1 as success. def : Pat<(int_ppc_tbegin i32:$R), (XORI (TBEGIN_RET(HTM_get_imm imm:$R)), 1)>; def : Pat<(int_ppc_tend i32:$R), (TEND (HTM_get_imm imm:$R))>; def : Pat<(int_ppc_tabort i32:$R), (TABORT $R)>; def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB), (TABORTWC (HTM_get_imm imm:$TO), $RA, $RB)>; def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI), (TABORTWCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>; def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB), (TABORTDC (HTM_get_imm imm:$TO), $RA, $RB)>; def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI), (TABORTDCI (HTM_get_imm imm:$TO), $RA, (HTM_get_imm imm:$SI))>; def : Pat<(int_ppc_tcheck), (TCHECK_RET)>; def : Pat<(int_ppc_treclaim i32:$RA), (TRECLAIM $RA)>; def : Pat<(int_ppc_trechkpt), (TRECHKPT)>; def : Pat<(int_ppc_tsr i32:$L), (TSR (HTM_get_imm imm:$L))>; def : Pat<(int_ppc_get_texasr), (MFSPR8 130)>; def : Pat<(int_ppc_get_texasru), (MFSPR8 131)>; def : Pat<(int_ppc_get_tfhar), (MFSPR8 128)>; def : Pat<(int_ppc_get_tfiar), (MFSPR8 129)>; def : Pat<(int_ppc_set_texasr i64:$V), (MTSPR8 130, $V)>; def : Pat<(int_ppc_set_texasru i64:$V), (MTSPR8 131, $V)>; def : Pat<(int_ppc_set_tfhar i64:$V), (MTSPR8 128, $V)>; def : Pat<(int_ppc_set_tfiar i64:$V), (MTSPR8 129, $V)>; // Extended mnemonics def : Pat<(int_ppc_tendall), (TEND 1)>; def : Pat<(int_ppc_tresume), (TSR 1)>; def : Pat<(int_ppc_tsuspend), (TSR 0)>; def : Pat<(i64 (int_ppc_ttest)), (RLDICL (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (TABORTWCI 0, (LI 0), 0), sub_32)), 36, 28)>; } // [HasHTM] def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>; def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>; def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>; def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;
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