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📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 P9InstrResources.td(37.36 KB)
📄 PPC.h(4.69 KB)
📄 PPC.td(32.37 KB)
📄 PPCAsmPrinter.cpp(70.77 KB)
📄 PPCBoolRetToInt.cpp(9.97 KB)
📄 PPCBranchCoalescing.cpp(30.16 KB)
📄 PPCBranchSelector.cpp(15.97 KB)
📄 PPCCCState.cpp(1.08 KB)
📄 PPCCCState.h(1.19 KB)
📄 PPCCTRLoops.cpp(6.68 KB)
📄 PPCCallingConv.cpp(6.19 KB)
📄 PPCCallingConv.h(1.97 KB)
📄 PPCCallingConv.td(16.32 KB)
📄 PPCEarlyReturn.cpp(7.14 KB)
📄 PPCExpandISEL.cpp(17.93 KB)
📄 PPCFastISel.cpp(85.51 KB)
📄 PPCFrameLowering.cpp(98.6 KB)
📄 PPCFrameLowering.h(7.46 KB)
📄 PPCHazardRecognizers.cpp(14.02 KB)
📄 PPCHazardRecognizers.h(3.83 KB)
📄 PPCISelDAGToDAG.cpp(256.88 KB)
📄 PPCISelLowering.cpp(669.73 KB)
📄 PPCISelLowering.h(55.9 KB)
📄 PPCInstr64Bit.td(75.68 KB)
📄 PPCInstrAltivec.td(77.68 KB)
📄 PPCInstrBuilder.h(1.5 KB)
📄 PPCInstrFormats.td(57.38 KB)
📄 PPCInstrHTM.td(5.48 KB)
📄 PPCInstrInfo.cpp(171.06 KB)
📄 PPCInstrInfo.h(29.06 KB)
📄 PPCInstrInfo.td(233.39 KB)
📄 PPCInstrPrefix.td(41.72 KB)
📄 PPCInstrQPX.td(57.56 KB)
📄 PPCInstrSPE.td(49.71 KB)
📄 PPCInstrVSX.td(223.48 KB)
📄 PPCLoopInstrFormPrep.cpp(33.45 KB)
📄 PPCLowerMASSVEntries.cpp(6.42 KB)
📄 PPCMCInstLower.cpp(6.62 KB)
📄 PPCMIPeephole.cpp(63.48 KB)
📄 PPCMachineFunctionInfo.cpp(2.59 KB)
📄 PPCMachineFunctionInfo.h(9.15 KB)
📄 PPCMachineScheduler.cpp(4.03 KB)
📄 PPCMachineScheduler.h(1.81 KB)
📄 PPCMacroFusion.cpp(6.68 KB)
📄 PPCMacroFusion.def(1.8 KB)
📄 PPCMacroFusion.h(886 B)
📄 PPCPerfectShuffle.h(397.57 KB)
📄 PPCPfmCounters.td(705 B)
📄 PPCPreEmitPeephole.cpp(13.36 KB)
📄 PPCQPXLoadSplat.cpp(5.31 KB)
📄 PPCReduceCRLogicals.cpp(28.66 KB)
📄 PPCRegisterInfo.cpp(51.93 KB)
📄 PPCRegisterInfo.h(6.61 KB)
📄 PPCRegisterInfo.td(14.24 KB)
📄 PPCSchedule.td(5.21 KB)
📄 PPCSchedule440.td(34.57 KB)
📄 PPCScheduleA2.td(7.85 KB)
📄 PPCScheduleE500.td(16.59 KB)
📄 PPCScheduleE500mc.td(20.89 KB)
📄 PPCScheduleE5500.td(23.62 KB)
📄 PPCScheduleG3.td(4.49 KB)
📄 PPCScheduleG4.td(5.42 KB)
📄 PPCScheduleG4Plus.td(6.45 KB)
📄 PPCScheduleG5.td(7.1 KB)
📄 PPCScheduleP7.td(22.26 KB)
📄 PPCScheduleP8.td(23.96 KB)
📄 PPCScheduleP9.td(12.27 KB)
📄 PPCSubtarget.cpp(7.58 KB)
📄 PPCSubtarget.h(13.21 KB)
📄 PPCTLSDynamicCall.cpp(6.53 KB)
📄 PPCTOCRegDeps.cpp(5.3 KB)
📄 PPCTargetMachine.cpp(18.94 KB)
📄 PPCTargetMachine.h(2.2 KB)
📄 PPCTargetObjectFile.cpp(2.45 KB)
📄 PPCTargetObjectFile.h(1.19 KB)
📄 PPCTargetStreamer.h(1.02 KB)
📄 PPCTargetTransformInfo.cpp(38.72 KB)
📄 PPCTargetTransformInfo.h(5.6 KB)
📄 PPCVSXCopy.cpp(5.68 KB)
📄 PPCVSXFMAMutate.cpp(15.12 KB)
📄 PPCVSXSwapRemoval.cpp(36.78 KB)
📄 README_P9.txt(22.25 KB)
📁 TargetInfo

Editing: PPCScheduleA2.td

//===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

// Primary reference:
// A2 Processor User's Manual.
// IBM (as updated in) 2010.

//===----------------------------------------------------------------------===//
// Functional units on the PowerPC A2 chip sets
//
def A2_XU     : FuncUnit; // A2_XU pipeline
def A2_FU     : FuncUnit; // FI pipeline

//
// This file defines the itinerary class data for the PPC A2 processor.
//
//===----------------------------------------------------------------------===//

def PPCA2Itineraries : ProcessorItineraries<
  [A2_XU, A2_FU], [], [
  InstrItinData<IIC_IntSimple,   [InstrStage<1, [A2_XU]>],
                                 [1, 0, 0]>,
  InstrItinData<IIC_IntGeneral,  [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0]>,
  InstrItinData<IIC_IntISEL,     [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0, 0]>,
  InstrItinData<IIC_IntCompare,  [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0]>,
  InstrItinData<IIC_IntDivW,     [InstrStage<1, [A2_XU]>],
                                 [39, 0, 0]>,
  InstrItinData<IIC_IntDivD,     [InstrStage<1, [A2_XU]>],
                                 [71, 0, 0]>,
  InstrItinData<IIC_IntMulHW,    [InstrStage<1, [A2_XU]>],
                                 [5, 0, 0]>,
  InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [A2_XU]>],
                                 [5, 0, 0]>,
  InstrItinData<IIC_IntMulLI,    [InstrStage<1, [A2_XU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_IntRotate,   [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0]>,
  InstrItinData<IIC_IntRotateD,  [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0]>,
  InstrItinData<IIC_IntRotateDI, [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0]>,
  InstrItinData<IIC_IntShift,    [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0]>,
  InstrItinData<IIC_IntTrapW,    [InstrStage<1, [A2_XU]>],
                                 [2, 0]>,
  InstrItinData<IIC_IntTrapD,    [InstrStage<1, [A2_XU]>],
                                 [2, 0]>,
  InstrItinData<IIC_BrB,         [InstrStage<1, [A2_XU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_BrCR,        [InstrStage<1, [A2_XU]>],
                                 [1, 0, 0]>,
  InstrItinData<IIC_BrMCR,       [InstrStage<1, [A2_XU]>],
                                 [5, 0, 0]>,
  InstrItinData<IIC_BrMCRX,      [InstrStage<1, [A2_XU]>],
                                 [1, 0, 0]>,
  InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [A2_XU]>],
                                 [1, 0, 0]>,
  InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [A2_XU]>],
                                 [1, 0, 0]>,
  InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [A2_XU]>],
                                 [1, 0, 0]>,
  InstrItinData<IIC_LdStLoad,    [InstrStage<1, [A2_XU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [A2_XU]>],
                                 [6, 8, 0, 0]>,
  InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [A2_XU]>],
                                 [6, 8, 0, 0]>,
  InstrItinData<IIC_LdStLDU,     [InstrStage<1, [A2_XU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_LdStLDUX,    [InstrStage<1, [A2_XU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_LdStStore,   [InstrStage<1, [A2_XU]>],
                                 [0, 0, 0]>,
  InstrItinData<IIC_LdStICBI,    [InstrStage<1, [A2_XU]>],
                                 [16, 0, 0]>,
  InstrItinData<IIC_LdStSTFD,    [InstrStage<1, [A2_XU]>],
                                 [0, 0, 0]>,
  InstrItinData<IIC_LdStSTFDU,   [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0, 0]>,
  InstrItinData<IIC_LdStLFD,     [InstrStage<1, [A2_XU]>],
                                 [7, 0, 0]>,
  InstrItinData<IIC_LdStLFDU,    [InstrStage<1, [A2_XU]>],
                                 [7, 9, 0, 0]>,
  InstrItinData<IIC_LdStLFDUX,   [InstrStage<1, [A2_XU]>],
                                 [7, 9, 0, 0]>,
  InstrItinData<IIC_LdStLHA,     [InstrStage<1, [A2_XU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [A2_XU]>],
                                 [6, 8, 0, 0]>,
  InstrItinData<IIC_LdStLHAUX,   [InstrStage<1, [A2_XU]>],
                                 [6, 8, 0, 0]>,
  InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [A2_XU]>],
                                 [82, 0, 0]>, // L2 latency
  InstrItinData<IIC_LdStSTD,     [InstrStage<1, [A2_XU]>],
                                 [0, 0, 0]>,
  InstrItinData<IIC_LdStSTU,     [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0, 0]>,
  InstrItinData<IIC_LdStSTUX,    [InstrStage<1, [A2_XU]>],
                                 [2, 0, 0, 0]>,
  InstrItinData<IIC_LdStSTDCX,   [InstrStage<1, [A2_XU]>],
                                 [82, 0, 0]>, // L2 latency
  InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [A2_XU]>],
                                 [82, 0, 0]>, // L2 latency
  InstrItinData<IIC_LdStSync,    [InstrStage<1, [A2_XU]>],
                                 [6]>,
  InstrItinData<IIC_SprISYNC,    [InstrStage<1, [A2_XU]>],
                                 [16]>,
  InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [A2_XU]>],
                                 [16, 0]>,
  InstrItinData<IIC_SprMFCR,     [InstrStage<1, [A2_XU]>],
                                 [6, 0]>,
  InstrItinData<IIC_SprMFCRF,    [InstrStage<1, [A2_XU]>],
                                 [1, 0]>,
  InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [A2_XU]>],
                                 [4, 0]>,
  InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [A2_XU]>],
                                 [6, 0]>,
  InstrItinData<IIC_SprMFTB,     [InstrStage<1, [A2_XU]>],
                                 [4, 0]>,
  InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [A2_XU]>],
                                 [6, 0]>,
  InstrItinData<IIC_SprRFI,      [InstrStage<1, [A2_XU]>],
                                 [16]>,
  InstrItinData<IIC_SprSC,       [InstrStage<1, [A2_XU]>],
                                 [16]>,
  InstrItinData<IIC_FPGeneral,   [InstrStage<1, [A2_FU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_FPAddSub,    [InstrStage<1, [A2_FU]>],
                                 [6, 0, 0]>,
  InstrItinData<IIC_FPCompare,   [InstrStage<1, [A2_FU]>],
                                 [5, 0, 0]>,
  InstrItinData<IIC_FPDivD,      [InstrStage<1, [A2_FU]>],
                                 [72, 0, 0]>,
  InstrItinData<IIC_FPDivS,      [InstrStage<1, [A2_FU]>],
                                 [59, 0, 0]>,
  InstrItinData<IIC_FPSqrtD,     [InstrStage<1, [A2_FU]>],
                                 [69, 0, 0]>,
  InstrItinData<IIC_FPSqrtS,     [InstrStage<1, [A2_FU]>],
                                 [65, 0, 0]>,
  InstrItinData<IIC_FPFused,     [InstrStage<1, [A2_FU]>],
                                 [6, 0, 0, 0]>,
  InstrItinData<IIC_FPRes,       [InstrStage<1, [A2_FU]>],
                                 [6, 0]>
]>;

// ===---------------------------------------------------------------------===//
// A2 machine model for scheduling and other instruction cost heuristics.

def PPCA2Model : SchedMachineModel {
  let IssueWidth = 1;  // 1 instruction is dispatched per cycle.
  let LoadLatency = 6; // Optimistic load latency assuming bypass.
                       // This is overriden by OperandCycles if the
                       // Itineraries are queried instead.
  let MispredictPenalty = 13;

let CompleteModel = 0;

let Itineraries = PPCA2Itineraries;
}

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