003 File Manager
Current Path:
/usr/src/contrib/llvm-project/llvm/lib/Target/PowerPC
usr
/
src
/
contrib
/
llvm-project
/
llvm
/
lib
/
Target
/
PowerPC
/
📁
..
📁
AsmParser
📁
Disassembler
📁
MCTargetDesc
📄
P9InstrResources.td
(37.36 KB)
📄
PPC.h
(4.69 KB)
📄
PPC.td
(32.37 KB)
📄
PPCAsmPrinter.cpp
(70.77 KB)
📄
PPCBoolRetToInt.cpp
(9.97 KB)
📄
PPCBranchCoalescing.cpp
(30.16 KB)
📄
PPCBranchSelector.cpp
(15.97 KB)
📄
PPCCCState.cpp
(1.08 KB)
📄
PPCCCState.h
(1.19 KB)
📄
PPCCTRLoops.cpp
(6.68 KB)
📄
PPCCallingConv.cpp
(6.19 KB)
📄
PPCCallingConv.h
(1.97 KB)
📄
PPCCallingConv.td
(16.32 KB)
📄
PPCEarlyReturn.cpp
(7.14 KB)
📄
PPCExpandISEL.cpp
(17.93 KB)
📄
PPCFastISel.cpp
(85.51 KB)
📄
PPCFrameLowering.cpp
(98.6 KB)
📄
PPCFrameLowering.h
(7.46 KB)
📄
PPCHazardRecognizers.cpp
(14.02 KB)
📄
PPCHazardRecognizers.h
(3.83 KB)
📄
PPCISelDAGToDAG.cpp
(256.88 KB)
📄
PPCISelLowering.cpp
(669.73 KB)
📄
PPCISelLowering.h
(55.9 KB)
📄
PPCInstr64Bit.td
(75.68 KB)
📄
PPCInstrAltivec.td
(77.68 KB)
📄
PPCInstrBuilder.h
(1.5 KB)
📄
PPCInstrFormats.td
(57.38 KB)
📄
PPCInstrHTM.td
(5.48 KB)
📄
PPCInstrInfo.cpp
(171.06 KB)
📄
PPCInstrInfo.h
(29.06 KB)
📄
PPCInstrInfo.td
(233.39 KB)
📄
PPCInstrPrefix.td
(41.72 KB)
📄
PPCInstrQPX.td
(57.56 KB)
📄
PPCInstrSPE.td
(49.71 KB)
📄
PPCInstrVSX.td
(223.48 KB)
📄
PPCLoopInstrFormPrep.cpp
(33.45 KB)
📄
PPCLowerMASSVEntries.cpp
(6.42 KB)
📄
PPCMCInstLower.cpp
(6.62 KB)
📄
PPCMIPeephole.cpp
(63.48 KB)
📄
PPCMachineFunctionInfo.cpp
(2.59 KB)
📄
PPCMachineFunctionInfo.h
(9.15 KB)
📄
PPCMachineScheduler.cpp
(4.03 KB)
📄
PPCMachineScheduler.h
(1.81 KB)
📄
PPCMacroFusion.cpp
(6.68 KB)
📄
PPCMacroFusion.def
(1.8 KB)
📄
PPCMacroFusion.h
(886 B)
📄
PPCPerfectShuffle.h
(397.57 KB)
📄
PPCPfmCounters.td
(705 B)
📄
PPCPreEmitPeephole.cpp
(13.36 KB)
📄
PPCQPXLoadSplat.cpp
(5.31 KB)
📄
PPCReduceCRLogicals.cpp
(28.66 KB)
📄
PPCRegisterInfo.cpp
(51.93 KB)
📄
PPCRegisterInfo.h
(6.61 KB)
📄
PPCRegisterInfo.td
(14.24 KB)
📄
PPCSchedule.td
(5.21 KB)
📄
PPCSchedule440.td
(34.57 KB)
📄
PPCScheduleA2.td
(7.85 KB)
📄
PPCScheduleE500.td
(16.59 KB)
📄
PPCScheduleE500mc.td
(20.89 KB)
📄
PPCScheduleE5500.td
(23.62 KB)
📄
PPCScheduleG3.td
(4.49 KB)
📄
PPCScheduleG4.td
(5.42 KB)
📄
PPCScheduleG4Plus.td
(6.45 KB)
📄
PPCScheduleG5.td
(7.1 KB)
📄
PPCScheduleP7.td
(22.26 KB)
📄
PPCScheduleP8.td
(23.96 KB)
📄
PPCScheduleP9.td
(12.27 KB)
📄
PPCSubtarget.cpp
(7.58 KB)
📄
PPCSubtarget.h
(13.21 KB)
📄
PPCTLSDynamicCall.cpp
(6.53 KB)
📄
PPCTOCRegDeps.cpp
(5.3 KB)
📄
PPCTargetMachine.cpp
(18.94 KB)
📄
PPCTargetMachine.h
(2.2 KB)
📄
PPCTargetObjectFile.cpp
(2.45 KB)
📄
PPCTargetObjectFile.h
(1.19 KB)
📄
PPCTargetStreamer.h
(1.02 KB)
📄
PPCTargetTransformInfo.cpp
(38.72 KB)
📄
PPCTargetTransformInfo.h
(5.6 KB)
📄
PPCVSXCopy.cpp
(5.68 KB)
📄
PPCVSXFMAMutate.cpp
(15.12 KB)
📄
PPCVSXSwapRemoval.cpp
(36.78 KB)
📄
README_P9.txt
(22.25 KB)
📁
TargetInfo
Editing: PPCSubtarget.cpp
//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements the PPC specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// #include "PPCSubtarget.h" #include "PPC.h" #include "PPCRegisterInfo.h" #include "PPCTargetMachine.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalValue.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Target/TargetMachine.h" #include <cstdlib> using namespace llvm; #define DEBUG_TYPE "ppc-subtarget" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "PPCGenSubtargetInfo.inc" static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness", cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden); static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned", cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"), cl::Hidden); static cl::opt<bool> EnableMachinePipeliner("ppc-enable-pipeliner", cl::desc("Enable Machine Pipeliner for PPC"), cl::init(false), cl::Hidden); PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { initializeEnvironment(); initSubtargetFeatures(CPU, FS); return *this; } PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const PPCTargetMachine &TM) : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), IsPPC64(TargetTriple.getArch() == Triple::ppc64 || TargetTriple.getArch() == Triple::ppc64le), TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), TLInfo(TM, *this) {} void PPCSubtarget::initializeEnvironment() { StackAlignment = Align(16); CPUDirective = PPC::DIR_NONE; HasMFOCRF = false; Has64BitSupport = false; Use64BitRegs = false; UseCRBits = false; HasHardFloat = false; HasAltivec = false; HasSPE = false; HasFPU = false; HasQPX = false; HasVSX = false; NeedsTwoConstNR = false; HasP8Vector = false; HasP8Altivec = false; HasP8Crypto = false; HasP9Vector = false; HasP9Altivec = false; HasP10Vector = false; HasPrefixInstrs = false; HasPCRelativeMemops = false; HasFCPSGN = false; HasFSQRT = false; HasFRE = false; HasFRES = false; HasFRSQRTE = false; HasFRSQRTES = false; HasRecipPrec = false; HasSTFIWX = false; HasLFIWAX = false; HasFPRND = false; HasFPCVT = false; HasISEL = false; HasBPERMD = false; HasExtDiv = false; HasCMPB = false; HasLDBRX = false; IsBookE = false; HasOnlyMSYNC = false; IsPPC4xx = false; IsPPC6xx = false; IsE500 = false; FeatureMFTB = false; AllowsUnalignedFPAccess = false; DeprecatedDST = false; HasICBT = false; HasInvariantFunctionDescriptors = false; HasPartwordAtomics = false; HasDirectMove = false; IsQPXStackUnaligned = false; HasHTM = false; HasFloat128 = false; HasFusion = false; HasAddiLoadFusion = false; HasAddisLoadFusion = false; IsISA3_0 = false; IsISA3_1 = false; UseLongCalls = false; SecurePlt = false; VectorsUseTwoUnits = false; UsePPCPreRASchedStrategy = false; UsePPCPostRASchedStrategy = false; PredictableSelectIsExpensive = false; HasPOPCNTD = POPCNTD_Unavailable; } void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { // Determine default and user specified characteristics std::string CPUName = std::string(CPU); if (CPUName.empty() || CPU == "generic") { // If cross-compiling with -march=ppc64le without -mcpu if (TargetTriple.getArch() == Triple::ppc64le) CPUName = "ppc64le"; else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe) CPUName = "e500"; else CPUName = "generic"; } // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); // Parse features string. ParseSubtargetFeatures(CPUName, FS); // If the user requested use of 64-bit regs, but the cpu selected doesn't // support it, ignore. if (IsPPC64 && has64BitSupport()) Use64BitRegs = true; if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || TargetTriple.isMusl()) SecurePlt = true; if (HasSPE && IsPPC64) report_fatal_error( "SPE is only supported for 32-bit targets.\n", false); if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU)) report_fatal_error( "SPE and traditional floating point cannot both be enabled.\n", false); // If not SPE, set standard FPU if (!HasSPE) HasFPU = true; // QPX requires a 32-byte aligned stack. Note that we need to do this if // we're compiling for a BG/Q system regardless of whether or not QPX // is enabled because external functions will assume this alignment. IsQPXStackUnaligned = QPXStackUnaligned; StackAlignment = getPlatformStackAlignment(); // Determine endianness. // FIXME: Part of the TargetMachine. IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); } bool PPCSubtarget::enableMachineScheduler() const { return true; } bool PPCSubtarget::enableMachinePipeliner() const { return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; } bool PPCSubtarget::useDFAforSMS() const { return false; } // This overrides the PostRAScheduler bit in the SchedModel for each CPU. bool PPCSubtarget::enablePostRAScheduler() const { return true; } PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { return TargetSubtargetInfo::ANTIDEP_ALL; } void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { CriticalPathRCs.clear(); CriticalPathRCs.push_back(isPPC64() ? &PPC::G8RCRegClass : &PPC::GPRCRegClass); } void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const { // The GenericScheduler that we use defaults to scheduling bottom up only. // We want to schedule from both the top and the bottom and so we set // OnlyBottomUp to false. // We want to do bi-directional scheduling since it provides a more balanced // schedule leading to better performance. Policy.OnlyBottomUp = false; // Spilling is generally expensive on all PPC cores, so always enable // register-pressure tracking. Policy.ShouldTrackPressure = true; } bool PPCSubtarget::useAA() const { return true; } bool PPCSubtarget::enableSubRegLiveness() const { return UseSubRegLiveness; } bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { // Large code model always uses the TOC even for local symbols. if (TM.getCodeModel() == CodeModel::Large) return true; if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) return false; return true; } bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); } bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); } bool PPCSubtarget::isUsingPCRelativeCalls() const { return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() && CodeModel::Medium == getTargetMachine().getCodeModel(); }
Upload File
Create Folder