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📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 P9InstrResources.td(37.36 KB)
📄 PPC.h(4.69 KB)
📄 PPC.td(32.37 KB)
📄 PPCAsmPrinter.cpp(70.77 KB)
📄 PPCBoolRetToInt.cpp(9.97 KB)
📄 PPCBranchCoalescing.cpp(30.16 KB)
📄 PPCBranchSelector.cpp(15.97 KB)
📄 PPCCCState.cpp(1.08 KB)
📄 PPCCCState.h(1.19 KB)
📄 PPCCTRLoops.cpp(6.68 KB)
📄 PPCCallingConv.cpp(6.19 KB)
📄 PPCCallingConv.h(1.97 KB)
📄 PPCCallingConv.td(16.32 KB)
📄 PPCEarlyReturn.cpp(7.14 KB)
📄 PPCExpandISEL.cpp(17.93 KB)
📄 PPCFastISel.cpp(85.51 KB)
📄 PPCFrameLowering.cpp(98.6 KB)
📄 PPCFrameLowering.h(7.46 KB)
📄 PPCHazardRecognizers.cpp(14.02 KB)
📄 PPCHazardRecognizers.h(3.83 KB)
📄 PPCISelDAGToDAG.cpp(256.88 KB)
📄 PPCISelLowering.cpp(669.73 KB)
📄 PPCISelLowering.h(55.9 KB)
📄 PPCInstr64Bit.td(75.68 KB)
📄 PPCInstrAltivec.td(77.68 KB)
📄 PPCInstrBuilder.h(1.5 KB)
📄 PPCInstrFormats.td(57.38 KB)
📄 PPCInstrHTM.td(5.48 KB)
📄 PPCInstrInfo.cpp(171.06 KB)
📄 PPCInstrInfo.h(29.06 KB)
📄 PPCInstrInfo.td(233.39 KB)
📄 PPCInstrPrefix.td(41.72 KB)
📄 PPCInstrQPX.td(57.56 KB)
📄 PPCInstrSPE.td(49.71 KB)
📄 PPCInstrVSX.td(223.48 KB)
📄 PPCLoopInstrFormPrep.cpp(33.45 KB)
📄 PPCLowerMASSVEntries.cpp(6.42 KB)
📄 PPCMCInstLower.cpp(6.62 KB)
📄 PPCMIPeephole.cpp(63.48 KB)
📄 PPCMachineFunctionInfo.cpp(2.59 KB)
📄 PPCMachineFunctionInfo.h(9.15 KB)
📄 PPCMachineScheduler.cpp(4.03 KB)
📄 PPCMachineScheduler.h(1.81 KB)
📄 PPCMacroFusion.cpp(6.68 KB)
📄 PPCMacroFusion.def(1.8 KB)
📄 PPCMacroFusion.h(886 B)
📄 PPCPerfectShuffle.h(397.57 KB)
📄 PPCPfmCounters.td(705 B)
📄 PPCPreEmitPeephole.cpp(13.36 KB)
📄 PPCQPXLoadSplat.cpp(5.31 KB)
📄 PPCReduceCRLogicals.cpp(28.66 KB)
📄 PPCRegisterInfo.cpp(51.93 KB)
📄 PPCRegisterInfo.h(6.61 KB)
📄 PPCRegisterInfo.td(14.24 KB)
📄 PPCSchedule.td(5.21 KB)
📄 PPCSchedule440.td(34.57 KB)
📄 PPCScheduleA2.td(7.85 KB)
📄 PPCScheduleE500.td(16.59 KB)
📄 PPCScheduleE500mc.td(20.89 KB)
📄 PPCScheduleE5500.td(23.62 KB)
📄 PPCScheduleG3.td(4.49 KB)
📄 PPCScheduleG4.td(5.42 KB)
📄 PPCScheduleG4Plus.td(6.45 KB)
📄 PPCScheduleG5.td(7.1 KB)
📄 PPCScheduleP7.td(22.26 KB)
📄 PPCScheduleP8.td(23.96 KB)
📄 PPCScheduleP9.td(12.27 KB)
📄 PPCSubtarget.cpp(7.58 KB)
📄 PPCSubtarget.h(13.21 KB)
📄 PPCTLSDynamicCall.cpp(6.53 KB)
📄 PPCTOCRegDeps.cpp(5.3 KB)
📄 PPCTargetMachine.cpp(18.94 KB)
📄 PPCTargetMachine.h(2.2 KB)
📄 PPCTargetObjectFile.cpp(2.45 KB)
📄 PPCTargetObjectFile.h(1.19 KB)
📄 PPCTargetStreamer.h(1.02 KB)
📄 PPCTargetTransformInfo.cpp(38.72 KB)
📄 PPCTargetTransformInfo.h(5.6 KB)
📄 PPCVSXCopy.cpp(5.68 KB)
📄 PPCVSXFMAMutate.cpp(15.12 KB)
📄 PPCVSXSwapRemoval.cpp(36.78 KB)
📄 README_P9.txt(22.25 KB)
📁 TargetInfo

Editing: PPCTLSDynamicCall.cpp

//===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into
// separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of
// which define GPR3.  A copy is added from GPR3 to the target virtual
// register of the original instruction.  The GETtlsADDR[32] is really
// a call instruction, so its target register is constrained to be GPR3.
// This is not true of ADDItls[gd]L[32], but there is a legacy linker
// optimization bug that requires the target register of the addi of
// a local- or general-dynamic TLS access sequence to be GPR3.
//
// This is done in a late pass so that TLS variable accesses can be
// fully commoned by MachineCSE.
//
//===----------------------------------------------------------------------===//

#include "PPC.h"
#include "PPCInstrBuilder.h"
#include "PPCInstrInfo.h"
#include "PPCTargetMachine.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/InitializePasses.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

using namespace llvm;

#define DEBUG_TYPE "ppc-tls-dynamic-call"

namespace {
  struct PPCTLSDynamicCall : public MachineFunctionPass {
    static char ID;
    PPCTLSDynamicCall() : MachineFunctionPass(ID) {
      initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry());
    }

const PPCInstrInfo *TII;
    LiveIntervals *LIS;

protected:
    bool processBlock(MachineBasicBlock &MBB) {
      bool Changed = false;
      bool NeedFence = true;
      bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();

for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
           I != IE;) {
        MachineInstr &MI = *I;

if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
            MI.getOpcode() != PPC::ADDItlsldLADDR &&
            MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
            MI.getOpcode() != PPC::ADDItlsldLADDR32) {

// Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
          // as scheduling fences, we skip creating fences if we already
          // have existing ADJCALLSTACKDOWN/UP to avoid nesting,
          // which causes verification error with -verify-machineinstrs.
          if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
            NeedFence = false;
          else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
            NeedFence = true;

++I;
          continue;
        }

LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n    " << MI);

Register OutReg = MI.getOperand(0).getReg();
        Register InReg = MI.getOperand(1).getReg();
        DebugLoc DL = MI.getDebugLoc();
        Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
        unsigned Opc1, Opc2;
        const Register OrigRegs[] = {OutReg, InReg, GPR3};

switch (MI.getOpcode()) {
        default:
          llvm_unreachable("Opcode inconsistency error");
        case PPC::ADDItlsgdLADDR:
          Opc1 = PPC::ADDItlsgdL;
          Opc2 = PPC::GETtlsADDR;
          break;
        case PPC::ADDItlsldLADDR:
          Opc1 = PPC::ADDItlsldL;
          Opc2 = PPC::GETtlsldADDR;
          break;
        case PPC::ADDItlsgdLADDR32:
          Opc1 = PPC::ADDItlsgdL32;
          Opc2 = PPC::GETtlsADDR32;
          break;
        case PPC::ADDItlsldLADDR32:
          Opc1 = PPC::ADDItlsldL32;
          Opc2 = PPC::GETtlsldADDR32;
          break;
        }

// We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
        // as scheduling fence to avoid it is scheduled before
        // mflr in the prologue and the address in LR is clobbered (PR25839).
        // We don't really need to save data to the stack - the clobbered
        // registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
        // gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
        if (NeedFence)
          BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
                                                              .addImm(0);

// Expand into two ops built prior to the existing instruction.
        MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
          .addReg(InReg);
        Addi->addOperand(MI.getOperand(2));

// The ADDItls* instruction is the first instruction in the
        // repair range.
        MachineBasicBlock::iterator First = I;
        --First;

MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
                              .addReg(GPR3));
        Call->addOperand(MI.getOperand(3));

if (NeedFence)
          BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);

BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
          .addReg(GPR3);

// The COPY is the last instruction in the repair range.
        MachineBasicBlock::iterator Last = I;
        --Last;

// Move past the original instruction and remove it.
        ++I;
        MI.removeFromParent();

// Repair the live intervals.
        LIS->repairIntervalsInRange(&MBB, First, Last, OrigRegs);
        Changed = true;
      }

return Changed;
    }

public:
    bool runOnMachineFunction(MachineFunction &MF) override {
      TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
      LIS = &getAnalysis<LiveIntervals>();

bool Changed = false;

for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
        MachineBasicBlock &B = *I++;
        if (processBlock(B))
          Changed = true;
      }

return Changed;
    }

void getAnalysisUsage(AnalysisUsage &AU) const override {
      AU.addRequired<LiveIntervals>();
      AU.addPreserved<LiveIntervals>();
      AU.addRequired<SlotIndexes>();
      AU.addPreserved<SlotIndexes>();
      MachineFunctionPass::getAnalysisUsage(AU);
    }
  };
}

INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE,
                      "PowerPC TLS Dynamic Call Fixup", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE,
                    "PowerPC TLS Dynamic Call Fixup", false, false)

char PPCTLSDynamicCall::ID = 0;
FunctionPass*
llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); }

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Editing: PPCTLSDynamicCall.cpp

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