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AsmParser
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Disassembler
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MCTargetDesc
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P9InstrResources.td
(37.36 KB)
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PPC.h
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PPC.td
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PPCAsmPrinter.cpp
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PPCBoolRetToInt.cpp
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PPCBranchCoalescing.cpp
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PPCBranchSelector.cpp
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PPCCCState.cpp
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PPCCCState.h
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PPCCTRLoops.cpp
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PPCCallingConv.cpp
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PPCCallingConv.h
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PPCCallingConv.td
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PPCEarlyReturn.cpp
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PPCExpandISEL.cpp
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PPCFastISel.cpp
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PPCFrameLowering.cpp
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PPCFrameLowering.h
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PPCHazardRecognizers.cpp
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PPCHazardRecognizers.h
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCISelLowering.h
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PPCInstr64Bit.td
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PPCInstrAltivec.td
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PPCInstrBuilder.h
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PPCInstrFormats.td
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PPCInstrHTM.td
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PPCInstrInfo.cpp
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PPCInstrInfo.h
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PPCInstrInfo.td
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PPCInstrPrefix.td
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PPCInstrQPX.td
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PPCInstrSPE.td
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PPCInstrVSX.td
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PPCLoopInstrFormPrep.cpp
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PPCLowerMASSVEntries.cpp
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PPCMCInstLower.cpp
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PPCMIPeephole.cpp
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PPCMachineFunctionInfo.cpp
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PPCMachineFunctionInfo.h
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PPCMachineScheduler.cpp
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PPCMachineScheduler.h
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PPCMacroFusion.cpp
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PPCMacroFusion.def
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PPCMacroFusion.h
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PPCPerfectShuffle.h
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PPCPfmCounters.td
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PPCPreEmitPeephole.cpp
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PPCQPXLoadSplat.cpp
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PPCReduceCRLogicals.cpp
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PPCRegisterInfo.cpp
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PPCRegisterInfo.h
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PPCRegisterInfo.td
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PPCSchedule.td
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PPCSchedule440.td
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PPCScheduleA2.td
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PPCScheduleE500.td
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PPCScheduleE500mc.td
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PPCScheduleE5500.td
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PPCScheduleG3.td
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PPCScheduleG4.td
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PPCScheduleG4Plus.td
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PPCScheduleG5.td
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PPCScheduleP7.td
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PPCScheduleP8.td
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PPCScheduleP9.td
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PPCSubtarget.cpp
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PPCSubtarget.h
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PPCTLSDynamicCall.cpp
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PPCTOCRegDeps.cpp
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PPCTargetMachine.cpp
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PPCTargetMachine.h
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PPCTargetObjectFile.cpp
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PPCTargetObjectFile.h
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PPCTargetStreamer.h
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PPCTargetTransformInfo.cpp
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PPCTargetTransformInfo.h
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PPCVSXCopy.cpp
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PPCVSXFMAMutate.cpp
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PPCVSXSwapRemoval.cpp
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README_P9.txt
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TargetInfo
Editing: PPCTargetTransformInfo.h
//===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// \file /// This file a TargetTransformInfo::Concept conforming object specific to the /// PPC target machine. It uses the target's detailed information to /// provide more precise answers to certain TTI queries, while letting the /// target independent and default TTI implementations handle the rest. /// //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H #define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H #include "PPCTargetMachine.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/CodeGen/TargetLowering.h" namespace llvm { class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> { typedef BasicTTIImplBase<PPCTTIImpl> BaseT; typedef TargetTransformInfo TTI; friend BaseT; const PPCSubtarget *ST; const PPCTargetLowering *TLI; const PPCSubtarget *getST() const { return ST; } const PPCTargetLowering *getTLI() const { return TLI; } bool mightUseCTR(BasicBlock *BB, TargetLibraryInfo *LibInfo, SmallPtrSetImpl<const Value *> &Visited); public: explicit PPCTTIImpl(const PPCTargetMachine *TM, const Function &F) : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} /// \name Scalar TTI Implementations /// @{ using BaseT::getIntImmCost; int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); unsigned getUserCost(const User *U, ArrayRef<const Value *> Operands, TTI::TargetCostKind CostKind); TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo); bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo); void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP); void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP); bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, TargetTransformInfo::LSRCost &C2); /// @} /// \name Vector TTI Implementations /// @{ bool useColdCCForColdCall(Function &F); bool enableAggressiveInterleaving(bool LoopHasReductions); TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const; bool enableInterleavedAccessVectorization(); enum PPCRegisterClass { GPRRC, FPRRC, VRRC, VSXRC }; unsigned getNumberOfRegisters(unsigned ClassID) const; unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const; const char* getRegisterClassName(unsigned ClassID) const; unsigned getRegisterBitWidth(bool Vector) const; unsigned getCacheLineSize() const override; unsigned getPrefetchDistance() const override; unsigned getMaxInterleaveFactor(unsigned VF); int vectorCostAdjustment(int Cost, unsigned Opcode, Type *Ty1, Type *Ty2); int getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, ArrayRef<const Value *> Args = ArrayRef<const Value *>(), const Instruction *CxtI = nullptr); int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp); int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::TargetCostKind CostKind, const Instruction *I = nullptr); int getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind); int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, TTI::TargetCostKind CostKind, const Instruction *I = nullptr); int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I = nullptr); int getInterleavedMemoryOpCost( unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, bool UseMaskForCond = false, bool UseMaskForGaps = false); unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind); /// @} }; } // end namespace llvm #endif
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