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📄 AMDGPU.h(11.46 KB)
📄 AMDGPU.td(36.97 KB)
📄 AMDGPUAliasAnalysis.cpp(5.58 KB)
📄 AMDGPUAliasAnalysis.h(3.32 KB)
📄 AMDGPUAlwaysInlinePass.cpp(4.83 KB)
📄 AMDGPUAnnotateKernelFeatures.cpp(11.94 KB)
📄 AMDGPUAnnotateUniformValues.cpp(6.13 KB)
📄 AMDGPUArgumentUsageInfo.cpp(7.66 KB)
📄 AMDGPUArgumentUsageInfo.h(4.81 KB)
📄 AMDGPUAsmPrinter.cpp(50.42 KB)
📄 AMDGPUAsmPrinter.h(5.13 KB)
📄 AMDGPUAtomicOptimizer.cpp(23.79 KB)
📄 AMDGPUCallLowering.cpp(28.66 KB)
📄 AMDGPUCallLowering.h(2.37 KB)
📄 AMDGPUCallingConv.td(7.33 KB)
📄 AMDGPUCodeGenPrepare.cpp(46.42 KB)
📄 AMDGPUCombine.td(2.79 KB)
📄 AMDGPUExportClustering.cpp(4.52 KB)
📄 AMDGPUExportClustering.h(533 B)
📄 AMDGPUFeatures.td(1.81 KB)
📄 AMDGPUFixFunctionBitcasts.cpp(1.87 KB)
📄 AMDGPUFrameLowering.cpp(1.98 KB)
📄 AMDGPUFrameLowering.h(1.39 KB)
📄 AMDGPUGISel.td(11.57 KB)
📄 AMDGPUGenRegisterBankInfo.def(5.83 KB)
📄 AMDGPUGlobalISelUtils.cpp(1.77 KB)
📄 AMDGPUGlobalISelUtils.h(2.07 KB)
📄 AMDGPUHSAMetadataStreamer.cpp(31.21 KB)
📄 AMDGPUHSAMetadataStreamer.h(5.46 KB)
📄 AMDGPUISelDAGToDAG.cpp(101.59 KB)
📄 AMDGPUISelLowering.cpp(168.65 KB)
📄 AMDGPUISelLowering.h(19.23 KB)
📄 AMDGPUInline.cpp(7.97 KB)
📄 AMDGPUInstrInfo.cpp(1.71 KB)
📄 AMDGPUInstrInfo.h(1.66 KB)
📄 AMDGPUInstrInfo.td(17.18 KB)
📄 AMDGPUInstructionSelector.cpp(128.53 KB)
📄 AMDGPUInstructionSelector.h(11.04 KB)
📄 AMDGPUInstructions.td(25.36 KB)
📄 AMDGPULegalizerInfo.cpp(149.32 KB)
📄 AMDGPULegalizerInfo.h(8.49 KB)
📄 AMDGPULibCalls.cpp(53.89 KB)
📄 AMDGPULibFunc.cpp(37.85 KB)
📄 AMDGPULibFunc.h(10.99 KB)
📄 AMDGPULowerIntrinsics.cpp(4.55 KB)
📄 AMDGPULowerKernelArguments.cpp(8.89 KB)
📄 AMDGPULowerKernelAttributes.cpp(7.78 KB)
📄 AMDGPUMCInstLower.cpp(14.27 KB)
📄 AMDGPUMachineCFGStructurizer.cpp(101.97 KB)
📄 AMDGPUMachineFunction.cpp(2.24 KB)
📄 AMDGPUMachineFunction.h(2.13 KB)
📄 AMDGPUMachineModuleInfo.cpp(1.34 KB)
📄 AMDGPUMachineModuleInfo.h(5.46 KB)
📄 AMDGPUMacroFusion.cpp(2.28 KB)
📄 AMDGPUMacroFusion.h(679 B)
📄 AMDGPUOpenCLEnqueuedBlockLowering.cpp(5.31 KB)
📄 AMDGPUPTNote.h(1.29 KB)
📄 AMDGPUPerfHintAnalysis.cpp(12.17 KB)
📄 AMDGPUPerfHintAnalysis.h(1.67 KB)
📄 AMDGPUPostLegalizerCombiner.cpp(12.02 KB)
📄 AMDGPUPreLegalizerCombiner.cpp(5.45 KB)
📄 AMDGPUPrintfRuntimeBinding.cpp(21.7 KB)
📄 AMDGPUPromoteAlloca.cpp(35.24 KB)
📄 AMDGPUPropagateAttributes.cpp(11.76 KB)
📄 AMDGPURegBankCombiner.cpp(5.36 KB)
📄 AMDGPURegisterBankInfo.cpp(161.67 KB)
📄 AMDGPURegisterBankInfo.h(7.41 KB)
📄 AMDGPURegisterBanks.td(921 B)
📄 AMDGPURewriteOutArguments.cpp(15.82 KB)
📄 AMDGPUSearchableTables.td(21.04 KB)
📄 AMDGPUSubtarget.cpp(29.62 KB)
📄 AMDGPUSubtarget.h(35.82 KB)
📄 AMDGPUTargetMachine.cpp(42.67 KB)
📄 AMDGPUTargetMachine.h(4.52 KB)
📄 AMDGPUTargetObjectFile.cpp(1.54 KB)
📄 AMDGPUTargetObjectFile.h(1.14 KB)
📄 AMDGPUTargetTransformInfo.cpp(39.07 KB)
📄 AMDGPUTargetTransformInfo.h(11.11 KB)
📄 AMDGPUUnifyDivergentExitNodes.cpp(13.84 KB)
📄 AMDGPUUnifyMetadata.cpp(4.46 KB)
📄 AMDILCFGStructurizer.cpp(56.32 KB)
📄 AMDKernelCodeT.h(32.84 KB)
📁 AsmParser
📄 BUFInstructions.td(110.75 KB)
📄 CaymanInstructions.td(7.93 KB)
📄 DSInstructions.td(52.37 KB)
📁 Disassembler
📄 EvergreenInstructions.td(28.24 KB)
📄 FLATInstructions.td(66.93 KB)
📄 GCNDPPCombine.cpp(19.92 KB)
📄 GCNHazardRecognizer.cpp(45.3 KB)
📄 GCNHazardRecognizer.h(3.96 KB)
📄 GCNILPSched.cpp(11.3 KB)
📄 GCNIterativeScheduler.cpp(20.62 KB)
📄 GCNIterativeScheduler.h(4.16 KB)
📄 GCNMinRegStrategy.cpp(8.47 KB)
📄 GCNNSAReassign.cpp(10.92 KB)
📄 GCNProcessors.td(4.84 KB)
📄 GCNRegBankReassign.cpp(26.68 KB)
📄 GCNRegPressure.cpp(16.27 KB)
📄 GCNRegPressure.h(9.15 KB)
📄 GCNSchedStrategy.cpp(21.67 KB)
📄 GCNSchedStrategy.h(3.77 KB)
📁 MCTargetDesc
📄 MIMGInstructions.td(39.85 KB)
📄 R600.td(1.51 KB)
📄 R600AsmPrinter.cpp(4.46 KB)
📄 R600AsmPrinter.h(1.5 KB)
📄 R600ClauseMergePass.cpp(7.38 KB)
📄 R600ControlFlowFinalizer.cpp(23.4 KB)
📄 R600Defines.h(4.25 KB)
📄 R600EmitClauseMarkers.cpp(12.1 KB)
📄 R600ExpandSpecialInstrs.cpp(10.11 KB)
📄 R600FrameLowering.cpp(1.83 KB)
📄 R600FrameLowering.h(1.25 KB)
📄 R600ISelLowering.cpp(81.88 KB)
📄 R600ISelLowering.h(4.8 KB)
📄 R600InstrFormats.td(11.58 KB)
📄 R600InstrInfo.cpp(49.47 KB)
📄 R600InstrInfo.h(13.7 KB)
📄 R600Instructions.td(55.13 KB)
📄 R600MachineFunctionInfo.cpp(551 B)
📄 R600MachineFunctionInfo.h(824 B)
📄 R600MachineScheduler.cpp(13.57 KB)
📄 R600MachineScheduler.h(2.53 KB)
📄 R600OpenCLImageTypeLoweringPass.cpp(11.75 KB)
📄 R600OptimizeVectorRegisters.cpp(13.4 KB)
📄 R600Packetizer.cpp(13.4 KB)
📄 R600Processors.td(4.42 KB)
📄 R600RegisterInfo.cpp(3.95 KB)
📄 R600RegisterInfo.h(2 KB)
📄 R600RegisterInfo.td(9.75 KB)
📄 R600Schedule.td(1.62 KB)
📄 R700Instructions.td(783 B)
📄 SIAddIMGInit.cpp(6.24 KB)
📄 SIAnnotateControlFlow.cpp(11.18 KB)
📄 SIDefines.h(20.86 KB)
📄 SIFixSGPRCopies.cpp(29.46 KB)
📄 SIFixVGPRCopies.cpp(2 KB)
📄 SIFixupVectorISel.cpp(8.75 KB)
📄 SIFoldOperands.cpp(54.56 KB)
📄 SIFormMemoryClauses.cpp(12.76 KB)
📄 SIFrameLowering.cpp(48.08 KB)
📄 SIFrameLowering.h(2.98 KB)
📄 SIISelLowering.cpp(423.43 KB)
📄 SIISelLowering.h(22.13 KB)
📄 SIInsertHardClauses.cpp(7.01 KB)
📄 SIInsertSkips.cpp(15.29 KB)
📄 SIInsertWaitcnts.cpp(58.33 KB)
📄 SIInstrFormats.td(9.44 KB)
📄 SIInstrInfo.cpp(247.15 KB)
📄 SIInstrInfo.h(41.24 KB)
📄 SIInstrInfo.td(90.7 KB)
📄 SIInstructions.td(77.7 KB)
📄 SILoadStoreOptimizer.cpp(76.21 KB)
📄 SILowerControlFlow.cpp(22.66 KB)
📄 SILowerI1Copies.cpp(27.83 KB)
📄 SILowerSGPRSpills.cpp(12.68 KB)
📄 SIMachineFunctionInfo.cpp(20.01 KB)
📄 SIMachineFunctionInfo.h(26.91 KB)
📄 SIMachineScheduler.cpp(69.44 KB)
📄 SIMachineScheduler.h(15.65 KB)
📄 SIMemoryLegalizer.cpp(45.84 KB)
📄 SIModeRegister.cpp(17.43 KB)
📄 SIOptimizeExecMasking.cpp(12.81 KB)
📄 SIOptimizeExecMaskingPreRA.cpp(11.13 KB)
📄 SIPeepholeSDWA.cpp(42.84 KB)
📄 SIPostRABundler.cpp(3.6 KB)
📄 SIPreAllocateWWMRegs.cpp(6.09 KB)
📄 SIPreEmitPeephole.cpp(10.51 KB)
📄 SIProgramInfo.h(2.04 KB)
📄 SIRegisterInfo.cpp(71.51 KB)
📄 SIRegisterInfo.h(13.04 KB)
📄 SIRegisterInfo.td(37.28 KB)
📄 SIRemoveShortExecBranches.cpp(4.96 KB)
📄 SISchedule.td(7.58 KB)
📄 SIShrinkInstructions.cpp(26.86 KB)
📄 SIWholeQuadMode.cpp(30.22 KB)
📄 SMInstructions.td(48.14 KB)
📄 SOPInstructions.td(60.51 KB)
📁 TargetInfo
📁 Utils
📄 VIInstrFormats.td(645 B)
📄 VOP1Instructions.td(35.53 KB)
📄 VOP2Instructions.td(65.04 KB)
📄 VOP3Instructions.td(53.14 KB)
📄 VOP3PInstructions.td(26.47 KB)
📄 VOPCInstructions.td(63.31 KB)
📄 VOPInstructions.td(23.76 KB)

Editing: R600InstrFormats.td

//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// R600 Instruction format definitions.
//
//===----------------------------------------------------------------------===//

def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;

def isR600toCayman : Predicate<
    "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;

class R600Pat<dag pattern, dag result> : AMDGPUPat<pattern, result> {
  let SubtargetPredicate = isR600toCayman;
}

class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
                InstrItinClass itin = NoItinerary>
    : AMDGPUInst <outs, ins, asm, pattern>, PredicateControl {

field bits<64> Inst;
  bit Trig = 0;
  bit Op3 = 0;
  bit isVector = 0;
  bits<2> FlagOperandIdx = 0;
  bit Op1 = 0;
  bit Op2 = 0;
  bit LDS_1A = 0;
  bit LDS_1A1D = 0;
  bit HasNativeOperands = 0;
  bit VTXInst = 0;
  bit TEXInst = 0;
  bit ALUInst = 0;
  bit IsExport = 0;
  bit LDS_1A2D = 0;

let SubtargetPredicate = isR600toCayman;
  let Namespace = "R600";
  let OutOperandList = outs;
  let InOperandList = ins;
  let AsmString = asm;
  let Pattern = pattern;
  let Itinerary = itin;

// No AsmMatcher support.
  let isCodeGenOnly = 1;

let TSFlags{4} = Trig;
  let TSFlags{5} = Op3;

// Vector instructions are instructions that must fill all slots in an
  // instruction group
  let TSFlags{6} = isVector;
  let TSFlags{8-7} = FlagOperandIdx;
  let TSFlags{9} = HasNativeOperands;
  let TSFlags{10} = Op1;
  let TSFlags{11} = Op2;
  let TSFlags{12} = VTXInst;
  let TSFlags{13} = TEXInst;
  let TSFlags{14} = ALUInst;
  let TSFlags{15} = LDS_1A;
  let TSFlags{16} = LDS_1A1D;
  let TSFlags{17} = IsExport;
  let TSFlags{18} = LDS_1A2D;
}

//===----------------------------------------------------------------------===//
// ALU instructions
//===----------------------------------------------------------------------===//

class R600_ALU_LDS_Word0 {
  field bits<32> Word0;

bits<11> src0;
  bits<1>  src0_rel;
  bits<11> src1;
  bits<1>  src1_rel;
  bits<3>  index_mode = 0;
  bits<2>  pred_sel;
  bits<1>  last;

bits<9>  src0_sel  = src0{8-0};
  bits<2>  src0_chan = src0{10-9};
  bits<9>  src1_sel  = src1{8-0};
  bits<2>  src1_chan = src1{10-9};

let Word0{8-0}   = src0_sel;
  let Word0{9}     = src0_rel;
  let Word0{11-10} = src0_chan;
  let Word0{21-13} = src1_sel;
  let Word0{22}    = src1_rel;
  let Word0{24-23} = src1_chan;
  let Word0{28-26} = index_mode;
  let Word0{30-29} = pred_sel;
  let Word0{31}    = last;
}

class R600ALU_Word0 : R600_ALU_LDS_Word0 {

bits<1>  src0_neg;
  bits<1>  src1_neg;

let Word0{12}    = src0_neg;
  let Word0{25}    = src1_neg;
}

class R600ALU_Word1 {
  field bits<32> Word1;

bits<11> dst;
  bits<3>  bank_swizzle;
  bits<1>  dst_rel;
  bits<1>  clamp;

bits<7>  dst_sel  = dst{6-0};
  bits<2>  dst_chan = dst{10-9};

let Word1{20-18} = bank_swizzle;
  let Word1{27-21} = dst_sel;
  let Word1{28}    = dst_rel;
  let Word1{30-29} = dst_chan;
  let Word1{31}    = clamp;
}

class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{

bits<1>  src0_abs;
  bits<1>  src1_abs;
  bits<1>  update_exec_mask;
  bits<1>  update_pred;
  bits<1>  write;
  bits<2>  omod;

let Word1{0}     = src0_abs;
  let Word1{1}     = src1_abs;
  let Word1{2}     = update_exec_mask;
  let Word1{3}     = update_pred;
  let Word1{4}     = write;
  let Word1{6-5}   = omod;
  let Word1{17-7}  = alu_inst;
}

class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{

bits<11> src2;
  bits<1>  src2_rel;
  bits<1>  src2_neg;

bits<9>  src2_sel = src2{8-0};
  bits<2>  src2_chan = src2{10-9};

let Word1{8-0}   = src2_sel;
  let Word1{9}     = src2_rel;
  let Word1{11-10} = src2_chan;
  let Word1{12}    = src2_neg;
  let Word1{17-13} = alu_inst;
}

class R600LDS_Word1 {
  field bits<32> Word1;

bits<11> src2;
  bits<9>  src2_sel  = src2{8-0};
  bits<2>  src2_chan = src2{10-9};
  bits<1>  src2_rel;
  // offset specifies the stride offset to the second set of data to be read
  // from.  This is a dword offset.
  bits<5>  alu_inst = 17; // OP3_INST_LDS_IDX_OP
  bits<3>  bank_swizzle;
  bits<6>  lds_op;
  bits<2>  dst_chan = 0;

let Word1{8-0}   = src2_sel;
  let Word1{9}     = src2_rel;
  let Word1{11-10} = src2_chan;
  let Word1{17-13} = alu_inst;
  let Word1{20-18} = bank_swizzle;
  let Word1{26-21} = lds_op;
  let Word1{30-29} = dst_chan;
}

/*
XXX: R600 subtarget uses a slightly different encoding than the other
subtargets.  We currently handle this in R600MCCodeEmitter, but we may
want to use these instruction classes in the future.

class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {

bits<1>  fog_merge;
  bits<10> alu_inst;

let Inst{37}    = fog_merge;
  let Inst{39-38} = omod;
  let Inst{49-40} = alu_inst;
}

class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {

bits<11> alu_inst;

let Inst{38-37} = omod;
  let Inst{49-39} = alu_inst;
}
*/

//===----------------------------------------------------------------------===//
// Vertex Fetch instructions
//===----------------------------------------------------------------------===//

class VTX_WORD0 {
  field bits<32> Word0;
  bits<7> src_gpr;
  bits<5> VC_INST;
  bits<2> FETCH_TYPE;
  bits<1> FETCH_WHOLE_QUAD;
  bits<8> buffer_id;
  bits<1> SRC_REL;
  bits<2> SRC_SEL_X;

let Word0{4-0}   = VC_INST;
  let Word0{6-5}   = FETCH_TYPE;
  let Word0{7}     = FETCH_WHOLE_QUAD;
  let Word0{15-8}  = buffer_id;
  let Word0{22-16} = src_gpr;
  let Word0{23}    = SRC_REL;
  let Word0{25-24} = SRC_SEL_X;
}

class VTX_WORD0_eg : VTX_WORD0 {

bits<6> MEGA_FETCH_COUNT;

let Word0{31-26} = MEGA_FETCH_COUNT;
}

class VTX_WORD0_cm : VTX_WORD0 {

bits<2> SRC_SEL_Y;
  bits<2> STRUCTURED_READ;
  bits<1> LDS_REQ;
  bits<1> COALESCED_READ;

let Word0{27-26} = SRC_SEL_Y;
  let Word0{29-28} = STRUCTURED_READ;
  let Word0{30}    = LDS_REQ;
  let Word0{31}    = COALESCED_READ;
}

class VTX_WORD1_GPR {
  field bits<32> Word1;
  bits<7> dst_gpr;
  bits<1> DST_REL;
  bits<3> DST_SEL_X;
  bits<3> DST_SEL_Y;
  bits<3> DST_SEL_Z;
  bits<3> DST_SEL_W;
  bits<1> USE_CONST_FIELDS;
  bits<6> DATA_FORMAT;
  bits<2> NUM_FORMAT_ALL;
  bits<1> FORMAT_COMP_ALL;
  bits<1> SRF_MODE_ALL;

let Word1{6-0} = dst_gpr;
  let Word1{7}    = DST_REL;
  let Word1{8}    = 0; // Reserved
  let Word1{11-9} = DST_SEL_X;
  let Word1{14-12} = DST_SEL_Y;
  let Word1{17-15} = DST_SEL_Z;
  let Word1{20-18} = DST_SEL_W;
  let Word1{21}    = USE_CONST_FIELDS;
  let Word1{27-22} = DATA_FORMAT;
  let Word1{29-28} = NUM_FORMAT_ALL;
  let Word1{30}    = FORMAT_COMP_ALL;
  let Word1{31}    = SRF_MODE_ALL;
}

//===----------------------------------------------------------------------===//
// Texture fetch instructions
//===----------------------------------------------------------------------===//

class TEX_WORD0 {
  field bits<32> Word0;

bits<5> TEX_INST;
  bits<2> INST_MOD;
  bits<1> FETCH_WHOLE_QUAD;
  bits<8> RESOURCE_ID;
  bits<7> SRC_GPR;
  bits<1> SRC_REL;
  bits<1> ALT_CONST;
  bits<2> RESOURCE_INDEX_MODE;
  bits<2> SAMPLER_INDEX_MODE;

let Word0{4-0} = TEX_INST;
  let Word0{6-5} = INST_MOD;
  let Word0{7} = FETCH_WHOLE_QUAD;
  let Word0{15-8} = RESOURCE_ID;
  let Word0{22-16} = SRC_GPR;
  let Word0{23} = SRC_REL;
  let Word0{24} = ALT_CONST;
  let Word0{26-25} = RESOURCE_INDEX_MODE;
  let Word0{28-27} = SAMPLER_INDEX_MODE;
}

class TEX_WORD1 {
  field bits<32> Word1;

bits<7> DST_GPR;
  bits<1> DST_REL;
  bits<3> DST_SEL_X;
  bits<3> DST_SEL_Y;
  bits<3> DST_SEL_Z;
  bits<3> DST_SEL_W;
  bits<7> LOD_BIAS;
  bits<1> COORD_TYPE_X;
  bits<1> COORD_TYPE_Y;
  bits<1> COORD_TYPE_Z;
  bits<1> COORD_TYPE_W;

let Word1{6-0} = DST_GPR;
  let Word1{7} = DST_REL;
  let Word1{11-9} = DST_SEL_X;
  let Word1{14-12} = DST_SEL_Y;
  let Word1{17-15} = DST_SEL_Z;
  let Word1{20-18} = DST_SEL_W;
  let Word1{27-21} = LOD_BIAS;
  let Word1{28} = COORD_TYPE_X;
  let Word1{29} = COORD_TYPE_Y;
  let Word1{30} = COORD_TYPE_Z;
  let Word1{31} = COORD_TYPE_W;
}

class TEX_WORD2 {
  field bits<32> Word2;

bits<5> OFFSET_X;
  bits<5> OFFSET_Y;
  bits<5> OFFSET_Z;
  bits<5> SAMPLER_ID;
  bits<3> SRC_SEL_X;
  bits<3> SRC_SEL_Y;
  bits<3> SRC_SEL_Z;
  bits<3> SRC_SEL_W;

let Word2{4-0} = OFFSET_X;
  let Word2{9-5} = OFFSET_Y;
  let Word2{14-10} = OFFSET_Z;
  let Word2{19-15} = SAMPLER_ID;
  let Word2{22-20} = SRC_SEL_X;
  let Word2{25-23} = SRC_SEL_Y;
  let Word2{28-26} = SRC_SEL_Z;
  let Word2{31-29} = SRC_SEL_W;
}

//===----------------------------------------------------------------------===//
// Control Flow Instructions
//===----------------------------------------------------------------------===//

class CF_WORD1_R600 {
  field bits<32> Word1;

bits<3> POP_COUNT;
  bits<5> CF_CONST;
  bits<2> COND;
  bits<3> COUNT;
  bits<6> CALL_COUNT;
  bits<1> COUNT_3;
  bits<1> END_OF_PROGRAM;
  bits<1> VALID_PIXEL_MODE;
  bits<7> CF_INST;
  bits<1> WHOLE_QUAD_MODE;
  bits<1> BARRIER;

let Word1{2-0} = POP_COUNT;
  let Word1{7-3} = CF_CONST;
  let Word1{9-8} = COND;
  let Word1{12-10} = COUNT;
  let Word1{18-13} = CALL_COUNT;
  let Word1{19} = COUNT_3;
  let Word1{21} = END_OF_PROGRAM;
  let Word1{22} = VALID_PIXEL_MODE;
  let Word1{29-23} = CF_INST;
  let Word1{30} = WHOLE_QUAD_MODE;
  let Word1{31} = BARRIER;
}

class CF_WORD0_EG {
  field bits<32> Word0;

bits<24> ADDR;
  bits<3> JUMPTABLE_SEL;

let Word0{23-0} = ADDR;
  let Word0{26-24} = JUMPTABLE_SEL;
}

class CF_WORD1_EG {
  field bits<32> Word1;

bits<3> POP_COUNT;
  bits<5> CF_CONST;
  bits<2> COND;
  bits<6> COUNT;
  bits<1> VALID_PIXEL_MODE;
  bits<1> END_OF_PROGRAM;
  bits<8> CF_INST;
  bits<1> BARRIER;

let Word1{2-0} = POP_COUNT;
  let Word1{7-3} = CF_CONST;
  let Word1{9-8} = COND;
  let Word1{15-10} = COUNT;
  let Word1{20} = VALID_PIXEL_MODE;
  let Word1{21} = END_OF_PROGRAM;
  let Word1{29-22} = CF_INST;
  let Word1{31} = BARRIER;
}

class CF_ALU_WORD0 {
  field bits<32> Word0;

bits<22> ADDR;
  bits<4> KCACHE_BANK0;
  bits<4> KCACHE_BANK1;
  bits<2> KCACHE_MODE0;

let Word0{21-0} = ADDR;
  let Word0{25-22} = KCACHE_BANK0;
  let Word0{29-26} = KCACHE_BANK1;
  let Word0{31-30} = KCACHE_MODE0;
}

class CF_ALU_WORD1 {
  field bits<32> Word1;

bits<2> KCACHE_MODE1;
  bits<8> KCACHE_ADDR0;
  bits<8> KCACHE_ADDR1;
  bits<7> COUNT;
  bits<1> ALT_CONST;
  bits<4> CF_INST;
  bits<1> WHOLE_QUAD_MODE;
  bits<1> BARRIER;

let Word1{1-0} = KCACHE_MODE1;
  let Word1{9-2} = KCACHE_ADDR0;
  let Word1{17-10} = KCACHE_ADDR1;
  let Word1{24-18} = COUNT;
  let Word1{25} = ALT_CONST;
  let Word1{29-26} = CF_INST;
  let Word1{30} = WHOLE_QUAD_MODE;
  let Word1{31} = BARRIER;
}

class CF_ALLOC_EXPORT_WORD0_RAT {
  field bits<32> Word0;

bits<4> rat_id;
  bits<6> rat_inst;
  bits<2> rim;
  bits<2> type;
  bits<7> rw_gpr;
  bits<1> rw_rel;
  bits<7> index_gpr;
  bits<2> elem_size;

let Word0{3-0}   = rat_id;
  let Word0{9-4}   = rat_inst;
  let Word0{10}    = 0; // Reserved
  let Word0{12-11} = rim;
  let Word0{14-13} = type;
  let Word0{21-15} = rw_gpr;
  let Word0{22}    = rw_rel;
  let Word0{29-23} = index_gpr;
  let Word0{31-30} = elem_size;
}

class CF_ALLOC_EXPORT_WORD1_BUF {
  field bits<32> Word1;

bits<12> array_size;
  bits<4>  comp_mask;
  bits<4>  burst_count;
  bits<1>  vpm;
  bits<1>  eop;
  bits<8>  cf_inst;
  bits<1>  mark;
  bits<1>  barrier;

let Word1{11-0} = array_size;
  let Word1{15-12} = comp_mask;
  let Word1{19-16} = burst_count;
  let Word1{20}    = vpm;
  let Word1{21}    = eop;
  let Word1{29-22} = cf_inst;
  let Word1{30}    = mark;
  let Word1{31}    = barrier;
}

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