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usr / src / contrib / llvm-project / llvm / lib / Target / Hexagon /

📁 ..
📁 AsmParser
📄 BitTracker.cpp(35.36 KB)
📄 BitTracker.h(17.25 KB)
📁 Disassembler
📄 Hexagon.h(1004 B)
📄 Hexagon.td(17.33 KB)
📄 HexagonArch.h(1.2 KB)
📄 HexagonAsmPrinter.cpp(26.65 KB)
📄 HexagonAsmPrinter.h(2.03 KB)
📄 HexagonBitSimplify.cpp(107.45 KB)
📄 HexagonBitTracker.cpp(39.88 KB)
📄 HexagonBitTracker.h(2.5 KB)
📄 HexagonBlockRanges.cpp(15.85 KB)
📄 HexagonBlockRanges.h(6.97 KB)
📄 HexagonBranchRelaxation.cpp(7.78 KB)
📄 HexagonCFGOptimizer.cpp(8.4 KB)
📄 HexagonCallingConv.td(4.46 KB)
📄 HexagonCommonGEP.cpp(41.47 KB)
📄 HexagonConstExtenders.cpp(70.64 KB)
📄 HexagonConstPropagation.cpp(97.75 KB)
📄 HexagonCopyToCombine.cpp(32.2 KB)
📄 HexagonDepArch.h(2.04 KB)
📄 HexagonDepArch.td(1.87 KB)
📄 HexagonDepDecoders.inc(2.55 KB)
📄 HexagonDepIICHVX.td(113.05 KB)
📄 HexagonDepIICScalar.td(224.12 KB)
📄 HexagonDepITypes.h(1.51 KB)
📄 HexagonDepITypes.td(1.91 KB)
📄 HexagonDepInstrFormats.td(91.89 KB)
📄 HexagonDepInstrInfo.td(1021.44 KB)
📄 HexagonDepMapAsm2Intrin.td(255.17 KB)
📄 HexagonDepMappings.td(64.27 KB)
📄 HexagonDepMask.h(51.94 KB)
📄 HexagonDepOperands.td(12.12 KB)
📄 HexagonDepTimingClasses.h(4.69 KB)
📄 HexagonEarlyIfConv.cpp(37.36 KB)
📄 HexagonExpandCondsets.cpp(48.55 KB)
📄 HexagonFixupHwLoops.cpp(6.54 KB)
📄 HexagonFrameLowering.cpp(97.16 KB)
📄 HexagonFrameLowering.h(7.85 KB)
📄 HexagonGenExtract.cpp(8.61 KB)
📄 HexagonGenInsert.cpp(53.24 KB)
📄 HexagonGenMux.cpp(12.71 KB)
📄 HexagonGenPredicate.cpp(16.25 KB)
📄 HexagonHardwareLoops.cpp(70.32 KB)
📄 HexagonHazardRecognizer.cpp(5.85 KB)
📄 HexagonHazardRecognizer.h(3.58 KB)
📄 HexagonIICHVX.td(1.21 KB)
📄 HexagonIICScalar.td(1.34 KB)
📄 HexagonISelDAGToDAG.cpp(78.63 KB)
📄 HexagonISelDAGToDAG.h(5.88 KB)
📄 HexagonISelDAGToDAGHVX.cpp(68.26 KB)
📄 HexagonISelLowering.cpp(134.65 KB)
📄 HexagonISelLowering.h(22.5 KB)
📄 HexagonISelLoweringHVX.cpp(70.57 KB)
📄 HexagonInstrFormats.td(12.04 KB)
📄 HexagonInstrFormatsV60.td(1.03 KB)
📄 HexagonInstrFormatsV65.td(1.54 KB)
📄 HexagonInstrInfo.cpp(161.08 KB)
📄 HexagonInstrInfo.h(25.31 KB)
📄 HexagonIntrinsics.td(19.21 KB)
📄 HexagonIntrinsicsV5.td(16.8 KB)
📄 HexagonIntrinsicsV60.td(28.9 KB)
📄 HexagonLoopIdiomRecognition.cpp(79.16 KB)
📄 HexagonMCInstLower.cpp(6.25 KB)
📄 HexagonMachineFunctionInfo.cpp(507 B)
📄 HexagonMachineFunctionInfo.h(3.32 KB)
📄 HexagonMachineScheduler.cpp(34.25 KB)
📄 HexagonMachineScheduler.h(8.66 KB)
📄 HexagonMapAsm2IntrinV62.gen.td(8.71 KB)
📄 HexagonMapAsm2IntrinV65.gen.td(12.43 KB)
📄 HexagonNewValueJump.cpp(25.57 KB)
📄 HexagonOperands.td(1.62 KB)
📄 HexagonOptAddrMode.cpp(29.37 KB)
📄 HexagonOptimizeSZextends.cpp(4.74 KB)
📄 HexagonPatterns.td(142.35 KB)
📄 HexagonPatternsHVX.td(22.06 KB)
📄 HexagonPatternsV65.td(2.96 KB)
📄 HexagonPeephole.cpp(10.18 KB)
📄 HexagonPseudo.td(21.62 KB)
📄 HexagonRDFOpt.cpp(9.94 KB)
📄 HexagonRegisterInfo.cpp(12.03 KB)
📄 HexagonRegisterInfo.h(2.88 KB)
📄 HexagonRegisterInfo.td(20.42 KB)
📄 HexagonSchedule.td(2.33 KB)
📄 HexagonScheduleV5.td(1.73 KB)
📄 HexagonScheduleV55.td(1.81 KB)
📄 HexagonScheduleV60.td(4.31 KB)
📄 HexagonScheduleV62.td(1.53 KB)
📄 HexagonScheduleV65.td(1.57 KB)
📄 HexagonScheduleV66.td(1.57 KB)
📄 HexagonScheduleV67.td(1.57 KB)
📄 HexagonScheduleV67T.td(2.51 KB)
📄 HexagonSelectionDAGInfo.cpp(2.35 KB)
📄 HexagonSelectionDAGInfo.h(1.24 KB)
📄 HexagonSplitConst32AndConst64.cpp(4.15 KB)
📄 HexagonSplitDouble.cpp(37.86 KB)
📄 HexagonStoreWidening.cpp(20.47 KB)
📄 HexagonSubtarget.cpp(20.97 KB)
📄 HexagonSubtarget.h(10.59 KB)
📄 HexagonTargetMachine.cpp(16 KB)
📄 HexagonTargetMachine.h(1.77 KB)
📄 HexagonTargetObjectFile.cpp(16.8 KB)
📄 HexagonTargetObjectFile.h(2.17 KB)
📄 HexagonTargetStreamer.h(1.2 KB)
📄 HexagonTargetTransformInfo.cpp(13.11 KB)
📄 HexagonTargetTransformInfo.h(6.27 KB)
📄 HexagonVExtract.cpp(6.64 KB)
📄 HexagonVLIWPacketizer.cpp(67.01 KB)
📄 HexagonVLIWPacketizer.h(6.09 KB)
📄 HexagonVectorLoopCarriedReuse.cpp(23.99 KB)
📄 HexagonVectorPrint.cpp(7.06 KB)
📁 MCTargetDesc
📄 RDFCopy.cpp(6.37 KB)
📄 RDFCopy.h(1.69 KB)
📄 RDFDeadCode.cpp(7.5 KB)
📄 RDFDeadCode.h(2.33 KB)
📁 TargetInfo

Editing: RDFCopy.cpp

//===- RDFCopy.cpp --------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// RDF-based copy propagation.
//
//===----------------------------------------------------------------------===//

#include "RDFCopy.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RDFGraph.h"
#include "llvm/CodeGen/RDFLiveness.h"
#include "llvm/CodeGen/RDFRegisters.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstdint>
#include <utility>

using namespace llvm;
using namespace rdf;

#ifndef NDEBUG
static cl::opt<unsigned> CpLimit("rdf-cp-limit", cl::init(0), cl::Hidden);
static unsigned CpCount = 0;
#endif

bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
  unsigned Opc = MI->getOpcode();
  switch (Opc) {
    case TargetOpcode::COPY: {
      const MachineOperand &Dst = MI->getOperand(0);
      const MachineOperand &Src = MI->getOperand(1);
      RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
      RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
      assert(Register::isPhysicalRegister(DstR.Reg));
      assert(Register::isPhysicalRegister(SrcR.Reg));
      const TargetRegisterInfo &TRI = DFG.getTRI();
      if (TRI.getMinimalPhysRegClass(DstR.Reg) !=
          TRI.getMinimalPhysRegClass(SrcR.Reg))
        return false;
      EM.insert(std::make_pair(DstR, SrcR));
      return true;
    }
    case TargetOpcode::REG_SEQUENCE:
      llvm_unreachable("Unexpected REG_SEQUENCE");
  }
  return false;
}

void CopyPropagation::recordCopy(NodeAddr<StmtNode*> SA, EqualityMap &EM) {
  CopyMap.insert(std::make_pair(SA.Id, EM));
  Copies.push_back(SA.Id);
}

bool CopyPropagation::scanBlock(MachineBasicBlock *B) {
  bool Changed = false;
  NodeAddr<BlockNode*> BA = DFG.findBlock(B);

for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) {
    if (DFG.IsCode<NodeAttrs::Stmt>(IA)) {
      NodeAddr<StmtNode*> SA = IA;
      EqualityMap EM;
      if (interpretAsCopy(SA.Addr->getCode(), EM))
        recordCopy(SA, EM);
    }
  }

MachineDomTreeNode *N = MDT.getNode(B);
  for (auto I : *N)
    Changed |= scanBlock(I->getBlock());

return Changed;
}

NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR,
      NodeAddr<InstrNode*> IA) {
  NodeAddr<RefNode*> RA = L.getNearestAliasedRef(RefRR, IA);
  if (RA.Id != 0) {
    if (RA.Addr->getKind() == NodeAttrs::Def)
      return RA.Id;
    assert(RA.Addr->getKind() == NodeAttrs::Use);
    if (NodeId RD = RA.Addr->getReachingDef())
      return RD;
  }
  return 0;
}

bool CopyPropagation::run() {
  scanBlock(&DFG.getMF().front());

if (trace()) {
    dbgs() << "Copies:\n";
    for (NodeId I : Copies) {
      dbgs() << "Instr: " << *DFG.addr<StmtNode*>(I).Addr->getCode();
      dbgs() << "   eq: {";
      for (auto J : CopyMap[I])
        dbgs() << ' ' << Print<RegisterRef>(J.first, DFG) << '='
               << Print<RegisterRef>(J.second, DFG);
      dbgs() << " }\n";
    }
  }

bool Changed = false;
#ifndef NDEBUG
  bool HasLimit = CpLimit.getNumOccurrences() > 0;
#endif

auto MinPhysReg = [this] (RegisterRef RR) -> unsigned {
    const TargetRegisterInfo &TRI = DFG.getTRI();
    const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg);
    if ((RC.LaneMask & RR.Mask) == RC.LaneMask)
      return RR.Reg;
    for (MCSubRegIndexIterator S(RR.Reg, &TRI); S.isValid(); ++S)
      if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex()))
        return S.getSubReg();
    llvm_unreachable("Should have found a register");
    return 0;
  };

for (NodeId C : Copies) {
#ifndef NDEBUG
    if (HasLimit && CpCount >= CpLimit)
      break;
#endif
    auto SA = DFG.addr<InstrNode*>(C);
    auto FS = CopyMap.find(SA.Id);
    if (FS == CopyMap.end())
      continue;

EqualityMap &EM = FS->second;
    for (NodeAddr<DefNode*> DA : SA.Addr->members_if(DFG.IsDef, DFG)) {
      RegisterRef DR = DA.Addr->getRegRef(DFG);
      auto FR = EM.find(DR);
      if (FR == EM.end())
        continue;
      RegisterRef SR = FR->second;
      if (DR == SR)
        continue;

NodeId AtCopy = getLocalReachingDef(SR, SA);

for (NodeId N = DA.Addr->getReachedUse(), NextN; N; N = NextN) {
        auto UA = DFG.addr<UseNode*>(N);
        NextN = UA.Addr->getSibling();
        uint16_t F = UA.Addr->getFlags();
        if ((F & NodeAttrs::PhiRef) || (F & NodeAttrs::Fixed))
          continue;
        if (UA.Addr->getRegRef(DFG) != DR)
          continue;

NodeAddr<InstrNode*> IA = UA.Addr->getOwner(DFG);
        assert(DFG.IsCode<NodeAttrs::Stmt>(IA));
        NodeId AtUse = getLocalReachingDef(SR, IA);
        if (AtCopy != AtUse)
          continue;

MachineOperand &Op = UA.Addr->getOp();
        if (Op.isTied())
          continue;
        if (trace()) {
          dbgs() << "Can replace " << Print<RegisterRef>(DR, DFG)
                 << " with " << Print<RegisterRef>(SR, DFG) << " in "
                 << *NodeAddr<StmtNode*>(IA).Addr->getCode();
        }

unsigned NewReg = MinPhysReg(SR);
        Op.setReg(NewReg);
        Op.setSubReg(0);
        DFG.unlinkUse(UA, false);
        if (AtCopy != 0) {
          UA.Addr->linkToDef(UA.Id, DFG.addr<DefNode*>(AtCopy));
        } else {
          UA.Addr->setReachingDef(0);
          UA.Addr->setSibling(0);
        }

Changed = true;
  #ifndef NDEBUG
        if (HasLimit && CpCount >= CpLimit)
          break;
        CpCount++;
  #endif

auto FC = CopyMap.find(IA.Id);
        if (FC != CopyMap.end()) {
          // Update the EM map in the copy's entry.
          auto &M = FC->second;
          for (auto &J : M) {
            if (J.second != DR)
              continue;
            J.second = SR;
            break;
          }
        }
      } // for (N in reached-uses)
    } // for (DA in defs)
  } // for (C in Copies)

return Changed;
}

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Editing: RDFCopy.cpp

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