File Manager

003 File Manager

Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc

usr / src / contrib / llvm-project / llvm / lib / Target / RISCV / MCTargetDesc /

📁 ..
📄 RISCVAsmBackend.cpp(16.91 KB)
📄 RISCVAsmBackend.h(4.58 KB)
📄 RISCVELFObjectWriter.cpp(5.06 KB)
📄 RISCVELFStreamer.cpp(5.48 KB)
📄 RISCVELFStreamer.h(3.43 KB)
📄 RISCVFixupKinds.h(3.71 KB)
📄 RISCVInstPrinter.cpp(6.35 KB)
📄 RISCVInstPrinter.h(2.81 KB)
📄 RISCVMCAsmInfo.cpp(1.91 KB)
📄 RISCVMCAsmInfo.h(1.01 KB)
📄 RISCVMCCodeEmitter.cpp(14.67 KB)
📄 RISCVMCExpr.cpp(6.73 KB)
📄 RISCVMCExpr.h(2.63 KB)
📄 RISCVMCTargetDesc.cpp(5.44 KB)
📄 RISCVMCTargetDesc.h(1.77 KB)
📄 RISCVTargetStreamer.cpp(4.04 KB)
📄 RISCVTargetStreamer.h(2.23 KB)

Editing: RISCVAsmBackend.h

//===-- RISCVAsmBackend.h - RISCV Assembler Backend -----------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H

#include "MCTargetDesc/RISCVFixupKinds.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "Utils/RISCVBaseInfo.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"

namespace llvm {
class MCAssembler;
class MCObjectTargetWriter;
class raw_ostream;

class RISCVAsmBackend : public MCAsmBackend {
  const MCSubtargetInfo &STI;
  uint8_t OSABI;
  bool Is64Bit;
  bool ForceRelocs = false;
  const MCTargetOptions &TargetOptions;
  RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;

public:
  RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
                  const MCTargetOptions &Options)
      : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
        TargetOptions(Options) {
    TargetABI = RISCVABI::computeTargetABI(
        STI.getTargetTriple(), STI.getFeatureBits(), Options.getABIName());
    RISCVFeatures::validate(STI.getTargetTriple(), STI.getFeatureBits());
  }
  ~RISCVAsmBackend() override {}

void setForceRelocs() { ForceRelocs = true; }

// Returns true if relocations will be forced for shouldForceRelocation by
  // default. This will be true if relaxation is enabled or had previously
  // been enabled.
  bool willForceRelocations() const {
    return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax];
  }

// Generate diff expression relocations if the relax feature is enabled or had
  // previously been enabled, otherwise it is safe for the assembler to
  // calculate these internally.
  bool requiresDiffExpressionRelocations() const override {
    return willForceRelocations();
  }

// Return Size with extra Nop Bytes for alignment directive in code section.
  bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
                                             unsigned &Size) override;

// Insert target specific fixup type for alignment directive in code section.
  bool shouldInsertFixupForCodeAlign(MCAssembler &Asm,
                                     const MCAsmLayout &Layout,
                                     MCAlignFragment &AF) override;

bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout,
                           const MCFixup &Fixup, const MCFragment *DF,
                           const MCValue &Target, uint64_t &Value,
                           bool &WasForced) override;

void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                  const MCValue &Target, MutableArrayRef<char> Data,
                  uint64_t Value, bool IsResolved,
                  const MCSubtargetInfo *STI) const override;

std::unique_ptr<MCObjectTargetWriter>
  createObjectTargetWriter() const override;

bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
                             const MCValue &Target) override;

bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
                            const MCRelaxableFragment *DF,
                            const MCAsmLayout &Layout) const override {
    llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
  }

bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
                                    uint64_t Value,
                                    const MCRelaxableFragment *DF,
                                    const MCAsmLayout &Layout,
                                    const bool WasForced) const override;

unsigned getNumFixupKinds() const override {
    return RISCV::NumTargetFixupKinds;
  }

Optional<MCFixupKind> getFixupKind(StringRef Name) const override;

const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;

bool mayNeedRelaxation(const MCInst &Inst,
                         const MCSubtargetInfo &STI) const override;
  unsigned getRelaxedOpcode(unsigned Op) const;

void relaxInstruction(MCInst &Inst,
                        const MCSubtargetInfo &STI) const override;

bool writeNopData(raw_ostream &OS, uint64_t Count) const override;

const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
  RISCVABI::ABI getTargetABI() const { return TargetABI; }
};
}

#endif

003 File Manager

Editing: RISCVAsmBackend.h

Upload File

Create Folder