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Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV

usr / src / contrib / llvm-project / llvm / lib / Target / RISCV /

📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 RISCV.h(1.82 KB)
📄 RISCV.td(10.89 KB)
📄 RISCVAsmPrinter.cpp(6.86 KB)
📄 RISCVCallLowering.cpp(1.48 KB)
📄 RISCVCallLowering.h(1.37 KB)
📄 RISCVCallingConv.td(2.27 KB)
📄 RISCVExpandAtomicPseudoInsts.cpp(21.27 KB)
📄 RISCVExpandPseudoInsts.cpp(6.94 KB)
📄 RISCVFrameLowering.cpp(28.44 KB)
📄 RISCVFrameLowering.h(3.1 KB)
📄 RISCVISelDAGToDAG.cpp(22.01 KB)
📄 RISCVISelDAGToDAG.h(2.21 KB)
📄 RISCVISelLowering.cpp(114.94 KB)
📄 RISCVISelLowering.h(10.3 KB)
📄 RISCVInstrFormats.td(10.36 KB)
📄 RISCVInstrFormatsC.td(4.98 KB)
📄 RISCVInstrFormatsV.td(7.57 KB)
📄 RISCVInstrInfo.cpp(26.69 KB)
📄 RISCVInstrInfo.h(5.88 KB)
📄 RISCVInstrInfo.td(45.57 KB)
📄 RISCVInstrInfoA.td(17.37 KB)
📄 RISCVInstrInfoB.td(47.16 KB)
📄 RISCVInstrInfoC.td(33.8 KB)
📄 RISCVInstrInfoD.td(15.36 KB)
📄 RISCVInstrInfoF.td(17.58 KB)
📄 RISCVInstrInfoM.td(4.17 KB)
📄 RISCVInstrInfoV.td(36.31 KB)
📄 RISCVInstructionSelector.cpp(3.18 KB)
📄 RISCVLegalizerInfo.cpp(870 B)
📄 RISCVLegalizerInfo.h(1000 B)
📄 RISCVMCInstLower.cpp(4.3 KB)
📄 RISCVMachineFunctionInfo.h(2.43 KB)
📄 RISCVMergeBaseOffset.cpp(11.06 KB)
📄 RISCVRegisterBankInfo.cpp(1.04 KB)
📄 RISCVRegisterBankInfo.h(1.22 KB)
📄 RISCVRegisterBanks.td(537 B)
📄 RISCVRegisterInfo.cpp(7.31 KB)
📄 RISCVRegisterInfo.h(2.11 KB)
📄 RISCVRegisterInfo.td(12.85 KB)
📄 RISCVSchedRocket32.td(8.04 KB)
📄 RISCVSchedRocket64.td(8.24 KB)
📄 RISCVSchedule.td(7.34 KB)
📄 RISCVSubtarget.cpp(2.63 KB)
📄 RISCVSubtarget.h(5.37 KB)
📄 RISCVSystemOperands.td(11.83 KB)
📄 RISCVTargetMachine.cpp(6.17 KB)
📄 RISCVTargetMachine.h(1.81 KB)
📄 RISCVTargetObjectFile.cpp(4.13 KB)
📄 RISCVTargetObjectFile.h(1.66 KB)
📄 RISCVTargetTransformInfo.cpp(3.06 KB)
📄 RISCVTargetTransformInfo.h(2.02 KB)
📁 TargetInfo
📁 Utils

Editing: RISCVFrameLowering.h

//===-- RISCVFrameLowering.h - Define frame lowering for RISCV -*- C++ -*--===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class implements RISCV-specific bits of TargetFrameLowering class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H
#define LLVM_LIB_TARGET_RISCV_RISCVFRAMELOWERING_H

#include "llvm/CodeGen/TargetFrameLowering.h"

namespace llvm {
class RISCVSubtarget;

class RISCVFrameLowering : public TargetFrameLowering {
public:
  explicit RISCVFrameLowering(const RISCVSubtarget &STI)
      : TargetFrameLowering(StackGrowsDown,
                            /*StackAlignment=*/Align(16),
                            /*LocalAreaOffset=*/0),
        STI(STI) {}

void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;

int getFrameIndexReference(const MachineFunction &MF, int FI,
                             Register &FrameReg) const override;

void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                            RegScavenger *RS) const override;

void processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                           RegScavenger *RS) const override;

bool hasFP(const MachineFunction &MF) const override;

bool hasBP(const MachineFunction &MF) const;

bool hasReservedCallFrame(const MachineFunction &MF) const override;
  MachineBasicBlock::iterator
  eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MI) const override;
  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI,
                                 ArrayRef<CalleeSavedInfo> CSI,
                                 const TargetRegisterInfo *TRI) const override;
  bool
  restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MI,
                              MutableArrayRef<CalleeSavedInfo> CSI,
                              const TargetRegisterInfo *TRI) const override;

// Get the first stack adjustment amount for SplitSPAdjust.
  // Return 0 if we don't want to to split the SP adjustment in prologue and
  // epilogue.
  uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const;

bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
  bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;

protected:
  const RISCVSubtarget &STI;

private:
  void determineFrameLayout(MachineFunction &MF) const;
  void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                 const DebugLoc &DL, Register DestReg, Register SrcReg,
                 int64_t Val, MachineInstr::MIFlag Flag) const;
};
}
#endif

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Editing: RISCVFrameLowering.h

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