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usr / src / contrib / llvm-project / llvm / lib / Target / RISCV /

📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 RISCV.h(1.82 KB)
📄 RISCV.td(10.89 KB)
📄 RISCVAsmPrinter.cpp(6.86 KB)
📄 RISCVCallLowering.cpp(1.48 KB)
📄 RISCVCallLowering.h(1.37 KB)
📄 RISCVCallingConv.td(2.27 KB)
📄 RISCVExpandAtomicPseudoInsts.cpp(21.27 KB)
📄 RISCVExpandPseudoInsts.cpp(6.94 KB)
📄 RISCVFrameLowering.cpp(28.44 KB)
📄 RISCVFrameLowering.h(3.1 KB)
📄 RISCVISelDAGToDAG.cpp(22.01 KB)
📄 RISCVISelDAGToDAG.h(2.21 KB)
📄 RISCVISelLowering.cpp(114.94 KB)
📄 RISCVISelLowering.h(10.3 KB)
📄 RISCVInstrFormats.td(10.36 KB)
📄 RISCVInstrFormatsC.td(4.98 KB)
📄 RISCVInstrFormatsV.td(7.57 KB)
📄 RISCVInstrInfo.cpp(26.69 KB)
📄 RISCVInstrInfo.h(5.88 KB)
📄 RISCVInstrInfo.td(45.57 KB)
📄 RISCVInstrInfoA.td(17.37 KB)
📄 RISCVInstrInfoB.td(47.16 KB)
📄 RISCVInstrInfoC.td(33.8 KB)
📄 RISCVInstrInfoD.td(15.36 KB)
📄 RISCVInstrInfoF.td(17.58 KB)
📄 RISCVInstrInfoM.td(4.17 KB)
📄 RISCVInstrInfoV.td(36.31 KB)
📄 RISCVInstructionSelector.cpp(3.18 KB)
📄 RISCVLegalizerInfo.cpp(870 B)
📄 RISCVLegalizerInfo.h(1000 B)
📄 RISCVMCInstLower.cpp(4.3 KB)
📄 RISCVMachineFunctionInfo.h(2.43 KB)
📄 RISCVMergeBaseOffset.cpp(11.06 KB)
📄 RISCVRegisterBankInfo.cpp(1.04 KB)
📄 RISCVRegisterBankInfo.h(1.22 KB)
📄 RISCVRegisterBanks.td(537 B)
📄 RISCVRegisterInfo.cpp(7.31 KB)
📄 RISCVRegisterInfo.h(2.11 KB)
📄 RISCVRegisterInfo.td(12.85 KB)
📄 RISCVSchedRocket32.td(8.04 KB)
📄 RISCVSchedRocket64.td(8.24 KB)
📄 RISCVSchedule.td(7.34 KB)
📄 RISCVSubtarget.cpp(2.63 KB)
📄 RISCVSubtarget.h(5.37 KB)
📄 RISCVSystemOperands.td(11.83 KB)
📄 RISCVTargetMachine.cpp(6.17 KB)
📄 RISCVTargetMachine.h(1.81 KB)
📄 RISCVTargetObjectFile.cpp(4.13 KB)
📄 RISCVTargetObjectFile.h(1.66 KB)
📄 RISCVTargetTransformInfo.cpp(3.06 KB)
📄 RISCVTargetTransformInfo.h(2.02 KB)
📁 TargetInfo
📁 Utils

Editing: RISCVInstrFormatsC.td

//===-- RISCVInstrFormatsC.td - RISCV C Instruction Formats --*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
//  This file describes the RISC-V C extension instruction formats.
//
//===----------------------------------------------------------------------===//

class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
               list<dag> pattern, InstFormat format>
    : Instruction {
  field bits<16> Inst;
  // SoftFail is a field the disassembler can use to provide a way for
  // instructions to not match without killing the whole decode process. It is
  // mainly used for ARM, but Tablegen expects this field to exist or it fails
  // to build the decode table.
  field bits<16> SoftFail = 0;
  let Size = 2;

bits<2> Opcode = 0;

let Namespace = "RISCV";

dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString = opcodestr # "\t" # argstr;
  let Pattern = pattern;

let TSFlags{4-0} = format.Value;
}

class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
                 string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> {
  bits<5> rs1;
  bits<5> rs2;

let Inst{15-12} = funct4;
  let Inst{11-7} = rs1;
  let Inst{6-2} = rs2;
  let Inst{1-0} = opcode;
}

// The immediate value encoding differs for each instruction, so each subclass
// is responsible for setting the appropriate bits in the Inst field.
// The bits Inst{6-2} must be set for each instruction.
class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                 string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> {
  bits<10> imm;
  bits<5> rd;
  bits<5> rs1;

let Inst{15-13} = funct3;
  let Inst{12} = imm{5};
  let Inst{11-7} = rd;
  let Inst{1-0} = opcode;
}

// The immediate value encoding differs for each instruction, so each subclass
// is responsible for setting the appropriate bits in the Inst field.
// The bits Inst{12-7} must be set for each instruction.
class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                  string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> {
  bits<10> imm;
  bits<5> rs2;
  bits<5> rs1;

let Inst{15-13} = funct3;
  let Inst{6-2} = rs2;
  let Inst{1-0} = opcode;
}

class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                  string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> {
  bits<10> imm;
  bits<3> rd;

let Inst{15-13} = funct3;
  let Inst{4-2} = rd;
  let Inst{1-0} = opcode;
}

// The immediate value encoding differs for each instruction, so each subclass
// is responsible for setting the appropriate bits in the Inst field.
// The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                 string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> {
  bits<3> rd;
  bits<3> rs1;

let Inst{15-13} = funct3;
  let Inst{9-7} = rs1;
  let Inst{4-2} = rd;
  let Inst{1-0} = opcode;
}

// The immediate value encoding differs for each instruction, so each subclass
// is responsible for setting the appropriate bits in the Inst field.
// The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                 string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> {
  bits<3> rs2;
  bits<3> rs1;

let Inst{15-13} = funct3;
  let Inst{9-7} = rs1;
  let Inst{4-2} = rs2;
  let Inst{1-0} = opcode;
}

class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,
                 dag ins, string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> {
  bits<3> rs2;
  bits<3> rs1;

let Inst{15-10} = funct6;
  let Inst{9-7} = rs1;
  let Inst{6-5} = funct2;
  let Inst{4-2} = rs2;
  let Inst{1-0} = opcode;
}

class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                 string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> {
  bits<9> imm;
  bits<3> rs1;

let Inst{15-13} = funct3;
  let Inst{9-7} = rs1;
  let Inst{1-0} = opcode;
}

class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
                 string opcodestr, string argstr>
    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> {
  bits<11> offset;

let Inst{15-13} = funct3;
  let Inst{12} = offset{10};
  let Inst{11} = offset{3};
  let Inst{10-9} = offset{8-7};
  let Inst{8} = offset{9};
  let Inst{7} = offset{5};
  let Inst{6} = offset{6};
  let Inst{5-3} = offset{2-0};
  let Inst{2} = offset{4};
  let Inst{1-0} = opcode;
}

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Editing: RISCVInstrFormatsC.td

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