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Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV

usr / src / contrib / llvm-project / llvm / lib / Target / RISCV /

📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 RISCV.h(1.82 KB)
📄 RISCV.td(10.89 KB)
📄 RISCVAsmPrinter.cpp(6.86 KB)
📄 RISCVCallLowering.cpp(1.48 KB)
📄 RISCVCallLowering.h(1.37 KB)
📄 RISCVCallingConv.td(2.27 KB)
📄 RISCVExpandAtomicPseudoInsts.cpp(21.27 KB)
📄 RISCVExpandPseudoInsts.cpp(6.94 KB)
📄 RISCVFrameLowering.cpp(28.44 KB)
📄 RISCVFrameLowering.h(3.1 KB)
📄 RISCVISelDAGToDAG.cpp(22.01 KB)
📄 RISCVISelDAGToDAG.h(2.21 KB)
📄 RISCVISelLowering.cpp(114.94 KB)
📄 RISCVISelLowering.h(10.3 KB)
📄 RISCVInstrFormats.td(10.36 KB)
📄 RISCVInstrFormatsC.td(4.98 KB)
📄 RISCVInstrFormatsV.td(7.57 KB)
📄 RISCVInstrInfo.cpp(26.69 KB)
📄 RISCVInstrInfo.h(5.88 KB)
📄 RISCVInstrInfo.td(45.57 KB)
📄 RISCVInstrInfoA.td(17.37 KB)
📄 RISCVInstrInfoB.td(47.16 KB)
📄 RISCVInstrInfoC.td(33.8 KB)
📄 RISCVInstrInfoD.td(15.36 KB)
📄 RISCVInstrInfoF.td(17.58 KB)
📄 RISCVInstrInfoM.td(4.17 KB)
📄 RISCVInstrInfoV.td(36.31 KB)
📄 RISCVInstructionSelector.cpp(3.18 KB)
📄 RISCVLegalizerInfo.cpp(870 B)
📄 RISCVLegalizerInfo.h(1000 B)
📄 RISCVMCInstLower.cpp(4.3 KB)
📄 RISCVMachineFunctionInfo.h(2.43 KB)
📄 RISCVMergeBaseOffset.cpp(11.06 KB)
📄 RISCVRegisterBankInfo.cpp(1.04 KB)
📄 RISCVRegisterBankInfo.h(1.22 KB)
📄 RISCVRegisterBanks.td(537 B)
📄 RISCVRegisterInfo.cpp(7.31 KB)
📄 RISCVRegisterInfo.h(2.11 KB)
📄 RISCVRegisterInfo.td(12.85 KB)
📄 RISCVSchedRocket32.td(8.04 KB)
📄 RISCVSchedRocket64.td(8.24 KB)
📄 RISCVSchedule.td(7.34 KB)
📄 RISCVSubtarget.cpp(2.63 KB)
📄 RISCVSubtarget.h(5.37 KB)
📄 RISCVSystemOperands.td(11.83 KB)
📄 RISCVTargetMachine.cpp(6.17 KB)
📄 RISCVTargetMachine.h(1.81 KB)
📄 RISCVTargetObjectFile.cpp(4.13 KB)
📄 RISCVTargetObjectFile.h(1.66 KB)
📄 RISCVTargetTransformInfo.cpp(3.06 KB)
📄 RISCVTargetTransformInfo.h(2.02 KB)
📁 TargetInfo
📁 Utils

Editing: RISCVTargetTransformInfo.cpp

//===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#include "RISCVTargetTransformInfo.h"
#include "Utils/RISCVMatInt.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/TargetLowering.h"
using namespace llvm;

#define DEBUG_TYPE "riscvtti"

int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
                                TTI::TargetCostKind CostKind) {
  assert(Ty->isIntegerTy() &&
         "getIntImmCost can only estimate cost of materialising integers");

// We have a Zero register, so 0 is always free.
  if (Imm == 0)
    return TTI::TCC_Free;

// Otherwise, we check how many instructions it will take to materialise.
  const DataLayout &DL = getDataLayout();
  return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
                                    getST()->is64Bit());
}

int RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
                                Type *Ty, TTI::TargetCostKind CostKind) {
  assert(Ty->isIntegerTy() &&
         "getIntImmCost can only estimate cost of materialising integers");

// We have a Zero register, so 0 is always free.
  if (Imm == 0)
    return TTI::TCC_Free;

// Some instructions in RISC-V can take a 12-bit immediate. Some of these are
  // commutative, in others the immediate comes from a specific argument index.
  bool Takes12BitImm = false;
  unsigned ImmArgIdx = ~0U;

switch (Opcode) {
  case Instruction::GetElementPtr:
    // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
    // split up large offsets in GEP into better parts than ConstantHoisting
    // can.
    return TTI::TCC_Free;
  case Instruction::Add:
  case Instruction::And:
  case Instruction::Or:
  case Instruction::Xor:
  case Instruction::Mul:
    Takes12BitImm = true;
    break;
  case Instruction::Sub:
  case Instruction::Shl:
  case Instruction::LShr:
  case Instruction::AShr:
    Takes12BitImm = true;
    ImmArgIdx = 1;
    break;
  default:
    break;
  }

if (Takes12BitImm) {
    // Check immediate is the correct argument...
    if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
      // ... and fits into the 12-bit immediate.
      if (Imm.getMinSignedBits() <= 64 &&
          getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
        return TTI::TCC_Free;
      }
    }

// Otherwise, use the full materialisation cost.
    return getIntImmCost(Imm, Ty, CostKind);
  }

// By default, prevent hoisting.
  return TTI::TCC_Free;
}

int RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                      const APInt &Imm, Type *Ty,
                                      TTI::TargetCostKind CostKind) {
  // Prevent hoisting in unknown cases.
  return TTI::TCC_Free;
}

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Editing: RISCVTargetTransformInfo.cpp

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