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AccelTable.h
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Analysis.h
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AntiDepBreaker.h
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AsmPrinter.h
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AsmPrinterHandler.h
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AtomicExpandUtils.h
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BasicTTIImpl.h
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BuiltinGCs.h
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CSEConfigBase.h
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CalcSpillWeights.h
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CallingConvLower.h
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CommandFlags.h
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CostTable.h
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DAGCombine.h
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DFAPacketizer.h
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DIE.h
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DIEValue.def
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DbgEntityHistoryCalculator.h
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DebugHandlerBase.h
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DwarfStringPoolEntry.h
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EdgeBundles.h
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ExecutionDomainFix.h
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ExpandReductions.h
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FastISel.h
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FaultMaps.h
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FunctionLoweringInfo.h
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GCMetadata.h
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GCMetadataPrinter.h
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GCStrategy.h
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GlobalISel
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ISDOpcodes.h
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IndirectThunks.h
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IntrinsicLowering.h
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LatencyPriorityQueue.h
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LazyMachineBlockFrequencyInfo.h
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LexicalScopes.h
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LinkAllAsmWriterComponents.h
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LinkAllCodegenComponents.h
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LiveInterval.h
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LiveIntervalCalc.h
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LiveIntervalUnion.h
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LiveIntervals.h
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LivePhysRegs.h
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LiveRangeCalc.h
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LiveRangeEdit.h
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LiveRegMatrix.h
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LiveRegUnits.h
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LiveStacks.h
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LiveVariables.h
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LoopTraversal.h
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LowLevelType.h
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MBFIWrapper.h
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MIRFormatter.h
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MIRParser
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MIRPrinter.h
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MIRYamlMapping.h
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MachORelocation.h
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MachineBasicBlock.h
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MachineBlockFrequencyInfo.h
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MachineBranchProbabilityInfo.h
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MachineCombinerPattern.h
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MachineConstantPool.h
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MachineDominanceFrontier.h
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MachineDominators.h
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MachineFrameInfo.h
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MachineFunction.h
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MachineFunctionPass.h
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MachineInstr.h
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MachineInstrBuilder.h
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MachineInstrBundle.h
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MachineInstrBundleIterator.h
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MachineJumpTableInfo.h
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MachineLoopInfo.h
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MachineLoopUtils.h
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MachineMemOperand.h
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MachineModuleInfo.h
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MachineModuleInfoImpls.h
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MachineOperand.h
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MachineOptimizationRemarkEmitter.h
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MachineOutliner.h
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MachinePassRegistry.h
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MachinePipeliner.h
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MachinePostDominators.h
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MachineRegionInfo.h
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MachineRegisterInfo.h
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MachineSSAUpdater.h
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MachineScheduler.h
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MachineSizeOpts.h
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MachineTraceMetrics.h
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MacroFusion.h
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ModuloSchedule.h
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NonRelocatableStringpool.h
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PBQP
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PBQPRAConstraint.h
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ParallelCG.h
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Passes.h
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PreISelIntrinsicLowering.h
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PseudoSourceValue.h
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RDFGraph.h
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RDFLiveness.h
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RDFRegisters.h
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ReachingDefAnalysis.h
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RegAllocPBQP.h
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RegAllocRegistry.h
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Register.h
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RegisterClassInfo.h
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RegisterPressure.h
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RegisterScavenging.h
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RegisterUsageInfo.h
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ResourcePriorityQueue.h
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RuntimeLibcalls.h
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SDNodeProperties.td
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ScheduleDAG.h
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ScheduleDAGInstrs.h
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ScheduleDAGMutation.h
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ScheduleDFS.h
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ScheduleHazardRecognizer.h
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SchedulerRegistry.h
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ScoreboardHazardRecognizer.h
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SelectionDAG.h
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SelectionDAGAddressAnalysis.h
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SelectionDAGISel.h
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SelectionDAGNodes.h
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SelectionDAGTargetInfo.h
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SlotIndexes.h
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Spiller.h
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StackMaps.h
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StackProtector.h
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SwiftErrorValueTracking.h
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SwitchLoweringUtils.h
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TailDuplicator.h
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TargetCallingConv.h
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TargetFrameLowering.h
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TargetInstrInfo.h
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TargetLowering.h
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TargetLoweringObjectFileImpl.h
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TargetOpcodes.h
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TargetPassConfig.h
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TargetRegisterInfo.h
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TargetSchedule.h
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TargetSubtargetInfo.h
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UnreachableBlockElim.h
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ValueTypes.h
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ValueTypes.td
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VirtRegMap.h
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WasmEHFuncInfo.h
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WinEHFuncInfo.h
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Editing: Register.h
//===-- llvm/CodeGen/Register.h ---------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #ifndef LLVM_CODEGEN_REGISTER_H #define LLVM_CODEGEN_REGISTER_H #include "llvm/MC/MCRegister.h" #include <cassert> namespace llvm { /// Wrapper class representing virtual and physical registers. Should be passed /// by value. class Register { unsigned Reg; public: constexpr Register(unsigned Val = 0): Reg(Val) {} constexpr Register(MCRegister Val): Reg(Val) {} // Register numbers can represent physical registers, virtual registers, and // sometimes stack slots. The unsigned values are divided into these ranges: // // 0 Not a register, can be used as a sentinel. // [1;2^30) Physical registers assigned by TableGen. // [2^30;2^31) Stack slots. (Rarely used.) // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. // // Further sentinels can be allocated from the small negative integers. // DenseMapInfo<unsigned> uses -1u and -2u. static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF, "Reg isn't large enough to hold full range."); /// isStackSlot - Sometimes it is useful the be able to store a non-negative /// frame index in a variable that normally holds a register. isStackSlot() /// returns true if Reg is in the range used for stack slots. /// /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack /// slots, so if a variable may contains a stack slot, always check /// isStackSlot() first. /// static bool isStackSlot(unsigned Reg) { return MCRegister::isStackSlot(Reg); } /// Compute the frame index from a register value representing a stack slot. static int stackSlot2Index(unsigned Reg) { assert(isStackSlot(Reg) && "Not a stack slot"); return int(Reg - MCRegister::FirstStackSlot); } /// Convert a non-negative frame index to a stack slot register value. static unsigned index2StackSlot(int FI) { assert(FI >= 0 && "Cannot hold a negative frame index."); return FI + MCRegister::FirstStackSlot; } /// Return true if the specified register number is in /// the physical register namespace. static bool isPhysicalRegister(unsigned Reg) { return MCRegister::isPhysicalRegister(Reg); } /// Return true if the specified register number is in /// the virtual register namespace. static bool isVirtualRegister(unsigned Reg) { assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); return Reg & MCRegister::VirtualRegFlag; } /// Convert a virtual register number to a 0-based index. /// The first virtual register in a function will get the index 0. static unsigned virtReg2Index(unsigned Reg) { assert(isVirtualRegister(Reg) && "Not a virtual register"); return Reg & ~MCRegister::VirtualRegFlag; } /// Convert a 0-based index to a virtual register number. /// This is the inverse operation of VirtReg2IndexFunctor below. static unsigned index2VirtReg(unsigned Index) { assert(Index < (1u << 31) && "Index too large for virtual register range."); return Index | MCRegister::VirtualRegFlag; } /// Return true if the specified register number is in the virtual register /// namespace. bool isVirtual() const { return isVirtualRegister(Reg); } /// Return true if the specified register number is in the physical register /// namespace. bool isPhysical() const { return isPhysicalRegister(Reg); } /// Convert a virtual register number to a 0-based index. The first virtual /// register in a function will get the index 0. unsigned virtRegIndex() const { return virtReg2Index(Reg); } constexpr operator unsigned() const { return Reg; } unsigned id() const { return Reg; } operator MCRegister() const { return MCRegister(Reg); } bool isValid() const { return Reg != MCRegister::NoRegister; } /// Comparisons between register objects bool operator==(const Register &Other) const { return Reg == Other.Reg; } bool operator!=(const Register &Other) const { return Reg != Other.Reg; } bool operator==(const MCRegister &Other) const { return Reg == Other.id(); } bool operator!=(const MCRegister &Other) const { return Reg != Other.id(); } /// Comparisons against register constants. E.g. /// * R == AArch64::WZR /// * R == 0 /// * R == VirtRegMap::NO_PHYS_REG bool operator==(unsigned Other) const { return Reg == Other; } bool operator!=(unsigned Other) const { return Reg != Other; } bool operator==(int Other) const { return Reg == unsigned(Other); } bool operator!=(int Other) const { return Reg != unsigned(Other); } // MSVC requires that we explicitly declare these two as well. bool operator==(MCPhysReg Other) const { return Reg == unsigned(Other); } bool operator!=(MCPhysReg Other) const { return Reg != unsigned(Other); } }; // Provide DenseMapInfo for Register template<> struct DenseMapInfo<Register> { static inline unsigned getEmptyKey() { return DenseMapInfo<unsigned>::getEmptyKey(); } static inline unsigned getTombstoneKey() { return DenseMapInfo<unsigned>::getTombstoneKey(); } static unsigned getHashValue(const Register &Val) { return DenseMapInfo<unsigned>::getHashValue(Val.id()); } static bool isEqual(const Register &LHS, const Register &RHS) { return DenseMapInfo<unsigned>::isEqual(LHS.id(), RHS.id()); } }; } #endif // ifndef LLVM_CODEGEN_REGISTER_H
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