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AggressiveAntiDepBreaker.cpp
(37.23 KB)
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AggressiveAntiDepBreaker.h
(6.8 KB)
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AllocationOrder.cpp
(1.96 KB)
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AllocationOrder.h
(2.96 KB)
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Analysis.cpp
(32.62 KB)
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AsmPrinter
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AtomicExpandPass.cpp
(71.86 KB)
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BBSectionsPrepare.cpp
(18.8 KB)
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BasicTargetTransformInfo.cpp
(1.53 KB)
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BranchFolding.cpp
(77.92 KB)
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BranchFolding.h
(7.36 KB)
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BranchRelaxation.cpp
(19.45 KB)
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BreakFalseDeps.cpp
(9.79 KB)
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BuiltinGCs.cpp
(4.88 KB)
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CFGuardLongjmp.cpp
(3.73 KB)
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CFIInstrInserter.cpp
(17.53 KB)
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CalcSpillWeights.cpp
(10.22 KB)
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CallingConvLower.cpp
(10.4 KB)
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CodeGen.cpp
(5.28 KB)
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CodeGenPrepare.cpp
(295.01 KB)
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CommandFlags.cpp
(24.89 KB)
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CriticalAntiDepBreaker.cpp
(27.91 KB)
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CriticalAntiDepBreaker.h
(4.22 KB)
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DFAPacketizer.cpp
(10.91 KB)
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DeadMachineInstructionElim.cpp
(6.52 KB)
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DetectDeadLanes.cpp
(20.74 KB)
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DwarfEHPrepare.cpp
(9.01 KB)
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EarlyIfConversion.cpp
(37.51 KB)
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EdgeBundles.cpp
(3.21 KB)
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ExecutionDomainFix.cpp
(14.67 KB)
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ExpandMemCmp.cpp
(33.66 KB)
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ExpandPostRAPseudos.cpp
(7.28 KB)
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ExpandReductions.cpp
(7.23 KB)
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FEntryInserter.cpp
(1.81 KB)
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FaultMaps.cpp
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FinalizeISel.cpp
(2.65 KB)
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FixupStatepointCallerSaved.cpp
(11.06 KB)
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FuncletLayout.cpp
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GCMetadata.cpp
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GCMetadataPrinter.cpp
(748 B)
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GCRootLowering.cpp
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GCStrategy.cpp
(708 B)
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GlobalISel
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GlobalMerge.cpp
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HardwareLoops.cpp
(18.44 KB)
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IfConversion.cpp
(89.43 KB)
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ImplicitNullChecks.cpp
(25.14 KB)
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IndirectBrExpandPass.cpp
(7.79 KB)
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InlineSpiller.cpp
(58.24 KB)
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InterferenceCache.cpp
(8.83 KB)
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InterferenceCache.h
(7.22 KB)
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InterleavedAccessPass.cpp
(16.59 KB)
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InterleavedLoadCombinePass.cpp
(42.35 KB)
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IntrinsicLowering.cpp
(17.08 KB)
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LLVMTargetMachine.cpp
(10.25 KB)
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LatencyPriorityQueue.cpp
(5.64 KB)
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LazyMachineBlockFrequencyInfo.cpp
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LexicalScopes.cpp
(12.16 KB)
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LiveDebugValues.cpp
(78.98 KB)
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LiveDebugVariables.cpp
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LiveDebugVariables.h
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LiveInterval.cpp
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LiveIntervalCalc.cpp
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LiveIntervalUnion.cpp
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LiveIntervals.cpp
(64.59 KB)
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LivePhysRegs.cpp
(11.08 KB)
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LiveRangeCalc.cpp
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LiveRangeEdit.cpp
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LiveRangeShrink.cpp
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LiveRangeUtils.h
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LiveRegMatrix.cpp
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LiveRegUnits.cpp
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LiveStacks.cpp
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LiveVariables.cpp
(30.26 KB)
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LocalStackSlotAllocation.cpp
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LoopTraversal.cpp
(2.89 KB)
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LowLevelType.cpp
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LowerEmuTLS.cpp
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MBFIWrapper.cpp
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MIRCanonicalizerPass.cpp
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MIRNamerPass.cpp
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MIRParser
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MIRPrinter.cpp
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MIRPrintingPass.cpp
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MIRVRegNamerUtils.cpp
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MIRVRegNamerUtils.h
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MachineBasicBlock.cpp
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MachineBlockFrequencyInfo.cpp
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MachineBlockPlacement.cpp
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MachineBranchProbabilityInfo.cpp
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MachineCSE.cpp
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MachineCombiner.cpp
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MachineCopyPropagation.cpp
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MachineDebugify.cpp
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MachineDominanceFrontier.cpp
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MachineDominators.cpp
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MachineFrameInfo.cpp
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MachineFunction.cpp
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MachineFunctionPass.cpp
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MachineFunctionPrinterPass.cpp
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MachineInstr.cpp
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MachineInstrBundle.cpp
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MachineLICM.cpp
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MachineLoopInfo.cpp
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MachineLoopUtils.cpp
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MachineModuleInfo.cpp
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MachineModuleInfoImpls.cpp
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MachineOperand.cpp
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MachineOptimizationRemarkEmitter.cpp
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MachineOutliner.cpp
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MachinePipeliner.cpp
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MachinePostDominators.cpp
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MachineRegionInfo.cpp
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MachineRegisterInfo.cpp
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MachineSSAUpdater.cpp
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MachineScheduler.cpp
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MachineSink.cpp
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MachineSizeOpts.cpp
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MachineStripDebug.cpp
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MachineTraceMetrics.cpp
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MachineVerifier.cpp
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MacroFusion.cpp
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ModuloSchedule.cpp
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NonRelocatableStringpool.cpp
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OptimizePHIs.cpp
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PHIElimination.cpp
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PHIEliminationUtils.cpp
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PHIEliminationUtils.h
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ParallelCG.cpp
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PatchableFunction.cpp
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PeepholeOptimizer.cpp
(78.41 KB)
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PostRAHazardRecognizer.cpp
(3.5 KB)
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PostRASchedulerList.cpp
(24.31 KB)
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PreISelIntrinsicLowering.cpp
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ProcessImplicitDefs.cpp
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PrologEpilogInserter.cpp
(50.45 KB)
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PseudoSourceValue.cpp
(4.71 KB)
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RDFGraph.cpp
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RDFLiveness.cpp
(40.7 KB)
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RDFRegisters.cpp
(11.29 KB)
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ReachingDefAnalysis.cpp
(21.74 KB)
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RegAllocBase.cpp
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RegAllocBase.h
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RegAllocBasic.cpp
(11.33 KB)
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RegAllocFast.cpp
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RegAllocGreedy.cpp
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RegAllocPBQP.cpp
(33.14 KB)
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RegUsageInfoCollector.cpp
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RegUsageInfoPropagate.cpp
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RegisterClassInfo.cpp
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RegisterCoalescer.cpp
(151.71 KB)
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RegisterCoalescer.h
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RegisterPressure.cpp
(48.86 KB)
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RegisterScavenging.cpp
(27.48 KB)
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RegisterUsageInfo.cpp
(3.18 KB)
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RenameIndependentSubregs.cpp
(14.79 KB)
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ResetMachineFunctionPass.cpp
(3.48 KB)
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SafeStack.cpp
(34.12 KB)
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SafeStackLayout.cpp
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SafeStackLayout.h
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ScalarizeMaskedMemIntrin.cpp
(31.46 KB)
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ScheduleDAG.cpp
(21.34 KB)
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ScheduleDAGInstrs.cpp
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ScheduleDAGPrinter.cpp
(3.21 KB)
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ScoreboardHazardRecognizer.cpp
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SelectionDAG
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ShadowStackGCLowering.cpp
(14.16 KB)
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ShrinkWrap.cpp
(23.03 KB)
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SjLjEHPrepare.cpp
(18.93 KB)
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SlotIndexes.cpp
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SpillPlacement.cpp
(12.58 KB)
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SpillPlacement.h
(6.67 KB)
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SplitKit.cpp
(66.39 KB)
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SplitKit.h
(23.7 KB)
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StackColoring.cpp
(49.03 KB)
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StackMapLivenessAnalysis.cpp
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StackMaps.cpp
(19.74 KB)
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StackProtector.cpp
(22.94 KB)
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StackSlotColoring.cpp
(17.12 KB)
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SwiftErrorValueTracking.cpp
(11.37 KB)
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SwitchLoweringUtils.cpp
(18.33 KB)
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TailDuplication.cpp
(3.32 KB)
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TailDuplicator.cpp
(38.29 KB)
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TargetFrameLoweringImpl.cpp
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TargetInstrInfo.cpp
(51.1 KB)
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TargetLoweringBase.cpp
(82.53 KB)
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TargetLoweringObjectFileImpl.cpp
(80.52 KB)
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TargetOptionsImpl.cpp
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TargetPassConfig.cpp
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TargetRegisterInfo.cpp
(19.15 KB)
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TargetSchedule.cpp
(13.16 KB)
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TargetSubtargetInfo.cpp
(1.89 KB)
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TwoAddressInstructionPass.cpp
(62.08 KB)
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TypePromotion.cpp
(32.46 KB)
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UnreachableBlockElim.cpp
(7.48 KB)
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ValueTypes.cpp
(19.87 KB)
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VirtRegMap.cpp
(21.4 KB)
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WasmEHPrepare.cpp
(17.48 KB)
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WinEHPrepare.cpp
(51.16 KB)
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XRayInstrumentation.cpp
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Editing: RegisterCoalescer.h
//===- RegisterCoalescer.h - Register Coalescing Interface ------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file contains the abstract interface for register coalescers, // allowing them to interact with and query register allocators. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_CODEGEN_REGISTERCOALESCER_H #define LLVM_LIB_CODEGEN_REGISTERCOALESCER_H namespace llvm { class MachineInstr; class TargetRegisterClass; class TargetRegisterInfo; /// A helper class for register coalescers. When deciding if /// two registers can be coalesced, CoalescerPair can determine if a copy /// instruction would become an identity copy after coalescing. class CoalescerPair { const TargetRegisterInfo &TRI; /// The register that will be left after coalescing. It can be a /// virtual or physical register. unsigned DstReg = 0; /// The virtual register that will be coalesced into dstReg. unsigned SrcReg = 0; /// The sub-register index of the old DstReg in the new coalesced register. unsigned DstIdx = 0; /// The sub-register index of the old SrcReg in the new coalesced register. unsigned SrcIdx = 0; /// True when the original copy was a partial subregister copy. bool Partial = false; /// True when both regs are virtual and newRC is constrained. bool CrossClass = false; /// True when DstReg and SrcReg are reversed from the original /// copy instruction. bool Flipped = false; /// The register class of the coalesced register, or NULL if DstReg /// is a physreg. This register class may be a super-register of both /// SrcReg and DstReg. const TargetRegisterClass *NewRC = nullptr; public: CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {} /// Create a CoalescerPair representing a virtreg-to-physreg copy. /// No need to call setRegisters(). CoalescerPair(unsigned VirtReg, unsigned PhysReg, const TargetRegisterInfo &tri) : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} /// Set registers to match the copy instruction MI. Return /// false if MI is not a coalescable copy instruction. bool setRegisters(const MachineInstr*); /// Swap SrcReg and DstReg. Return false if swapping is impossible /// because DstReg is a physical register, or SubIdx is set. bool flip(); /// Return true if MI is a copy instruction that will become /// an identity copy after coalescing. bool isCoalescable(const MachineInstr*) const; /// Return true if DstReg is a physical register. bool isPhys() const { return !NewRC; } /// Return true if the original copy instruction did not copy /// the full register, but was a subreg operation. bool isPartial() const { return Partial; } /// Return true if DstReg is virtual and NewRC is a smaller /// register class than DstReg's. bool isCrossClass() const { return CrossClass; } /// Return true when getSrcReg is the register being defined by /// the original copy instruction. bool isFlipped() const { return Flipped; } /// Return the register (virtual or physical) that will remain /// after coalescing. unsigned getDstReg() const { return DstReg; } /// Return the virtual register that will be coalesced away. unsigned getSrcReg() const { return SrcReg; } /// Return the subregister index that DstReg will be coalesced into, or 0. unsigned getDstIdx() const { return DstIdx; } /// Return the subregister index that SrcReg will be coalesced into, or 0. unsigned getSrcIdx() const { return SrcIdx; } /// Return the register class of the coalesced register. const TargetRegisterClass *getNewRC() const { return NewRC; } }; } // end namespace llvm #endif // LLVM_LIB_CODEGEN_REGISTERCOALESCER_H
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