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📁 ..
📁 AsmParser
📄 DelaySlotFiller.cpp(14.86 KB)
📁 Disassembler
📄 LeonFeatures.td(2.12 KB)
📄 LeonPasses.cpp(5.78 KB)
📄 LeonPasses.h(2.59 KB)
📁 MCTargetDesc
📄 Sparc.h(5.28 KB)
📄 Sparc.td(7.33 KB)
📄 SparcAsmPrinter.cpp(16.24 KB)
📄 SparcCallingConv.td(5.66 KB)
📄 SparcFrameLowering.cpp(13.77 KB)
📄 SparcFrameLowering.h(2.4 KB)
📄 SparcISelDAGToDAG.cpp(14.22 KB)
📄 SparcISelLowering.cpp(133.64 KB)
📄 SparcISelLowering.h(9.48 KB)
📄 SparcInstr64Bit.td(21.58 KB)
📄 SparcInstrAliases.td(21.18 KB)
📄 SparcInstrFormats.td(10.36 KB)
📄 SparcInstrInfo.cpp(18.87 KB)
📄 SparcInstrInfo.h(4.13 KB)
📄 SparcInstrInfo.td(68.33 KB)
📄 SparcInstrVIS.td(11.1 KB)
📄 SparcMCInstLower.cpp(3.31 KB)
📄 SparcMachineFunctionInfo.cpp(476 B)
📄 SparcMachineFunctionInfo.h(1.92 KB)
📄 SparcRegisterInfo.cpp(8.22 KB)
📄 SparcRegisterInfo.h(1.73 KB)
📄 SparcRegisterInfo.td(13.94 KB)
📄 SparcSchedule.td(6.43 KB)
📄 SparcSubtarget.cpp(3.17 KB)
📄 SparcSubtarget.h(4.08 KB)
📄 SparcTargetMachine.cpp(7.77 KB)
📄 SparcTargetMachine.h(2.78 KB)
📄 SparcTargetObjectFile.cpp(1.85 KB)
📄 SparcTargetObjectFile.h(1.15 KB)
📁 TargetInfo

Editing: SparcInstrInfo.h

//===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the Sparc implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H
#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H

#include "SparcRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"

#define GET_INSTRINFO_HEADER
#include "SparcGenInstrInfo.inc"

namespace llvm {

class SparcSubtarget;

/// SPII - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
namespace SPII {
  enum {
    Pseudo = (1<<0),
    Load = (1<<1),
    Store = (1<<2),
    DelaySlot = (1<<3)
  };
}

class SparcInstrInfo : public SparcGenInstrInfo {
  const SparcRegisterInfo RI;
  const SparcSubtarget& Subtarget;
  virtual void anchor();
public:
  explicit SparcInstrInfo(SparcSubtarget &ST);

/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  /// such, whenever a client has an instance of instruction info, it should
  /// always be able to get register info as well (through this method).
  ///
  const SparcRegisterInfo &getRegisterInfo() const { return RI; }

/// isLoadFromStackSlot - If the specified machine instruction is a direct
  /// load from a stack slot, return the virtual or physical register number of
  /// the destination along with the FrameIndex of the loaded stack slot.  If
  /// not, return 0.  This predicate must return 0 if the instruction has
  /// any side effects other than loading from the stack slot.
  unsigned isLoadFromStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;

/// isStoreToStackSlot - If the specified machine instruction is a direct
  /// store to a stack slot, return the virtual or physical register number of
  /// the source reg along with the FrameIndex of the loaded stack slot.  If
  /// not, return 0.  This predicate must return 0 if the instruction has
  /// any side effects other than storing to the stack slot.
  unsigned isStoreToStackSlot(const MachineInstr &MI,
                              int &FrameIndex) const override;

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                     MachineBasicBlock *&FBB,
                     SmallVectorImpl<MachineOperand> &Cond,
                     bool AllowModify = false) const override;

unsigned removeBranch(MachineBasicBlock &MBB,
                        int *BytesRemoved = nullptr) const override;

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                        const DebugLoc &DL,
                        int *BytesAdded = nullptr) const override;

bool
  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
                   bool KillSrc) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI,
                           Register SrcReg, bool isKill, int FrameIndex,
                           const TargetRegisterClass *RC,
                           const TargetRegisterInfo *TRI) const override;

void loadRegFromStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI,
                            Register DestReg, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;

// Lower pseudo instructions after register allocation.
  bool expandPostRAPseudo(MachineInstr &MI) const override;
};

}

#endif

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