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📄 AccelTable.h(13.54 KB)
📄 Analysis.h(6.04 KB)
📄 AntiDepBreaker.h(3.78 KB)
📄 AsmPrinter.h(27.35 KB)
📄 AsmPrinterHandler.h(2.6 KB)
📄 AtomicExpandUtils.h(2.49 KB)
📄 BasicTTIImpl.h(73.64 KB)
📄 BuiltinGCs.h(1008 B)
📄 CSEConfigBase.h(1.09 KB)
📄 CalcSpillWeights.h(4.69 KB)
📄 CallingConvLower.h(21 KB)
📄 CommandFlags.h(3.65 KB)
📄 CostTable.h(1.87 KB)
📄 DAGCombine.h(606 B)
📄 DFAPacketizer.h(7.47 KB)
📄 DIE.h(32.19 KB)
📄 DIEValue.def(1.4 KB)
📄 DbgEntityHistoryCalculator.h(4.37 KB)
📄 DebugHandlerBase.h(4.68 KB)
📄 DwarfStringPoolEntry.h(2.18 KB)
📄 EdgeBundles.h(2.13 KB)
📄 ExecutionDomainFix.h(7.72 KB)
📄 ExpandReductions.h(726 B)
📄 FastISel.h(22.87 KB)
📄 FaultMaps.h(6.66 KB)
📄 FunctionLoweringInfo.h(9.68 KB)
📄 GCMetadata.h(7.24 KB)
📄 GCMetadataPrinter.h(2.46 KB)
📄 GCStrategy.h(5.25 KB)
📁 GlobalISel
📄 ISDOpcodes.h(52.75 KB)
📄 IndirectThunks.h(3.85 KB)
📄 IntrinsicLowering.h(1.67 KB)
📄 LatencyPriorityQueue.h(3.09 KB)
📄 LazyMachineBlockFrequencyInfo.h(2.82 KB)
📄 LexicalScopes.h(10.06 KB)
📄 LinkAllAsmWriterComponents.h(1.34 KB)
📄 LinkAllCodegenComponents.h(2.18 KB)
📄 LiveInterval.h(37.24 KB)
📄 LiveIntervalCalc.h(2.91 KB)
📄 LiveIntervalUnion.h(6.93 KB)
📄 LiveIntervals.h(19.86 KB)
📄 LivePhysRegs.h(7.51 KB)
📄 LiveRangeCalc.h(11.49 KB)
📄 LiveRangeEdit.h(10.45 KB)
📄 LiveRegMatrix.h(6.18 KB)
📄 LiveRegUnits.h(6.24 KB)
📄 LiveStacks.h(3.35 KB)
📄 LiveVariables.h(12.98 KB)
📄 LoopTraversal.h(4.38 KB)
📄 LowLevelType.h(1.28 KB)
📄 MBFIWrapper.h(1.58 KB)
📄 MIRFormatter.h(3.13 KB)
📁 MIRParser
📄 MIRPrinter.h(1.73 KB)
📄 MIRYamlMapping.h(23.95 KB)
📄 MachORelocation.h(2.19 KB)
📄 MachineBasicBlock.h(42.95 KB)
📄 MachineBlockFrequencyInfo.h(3.21 KB)
📄 MachineBranchProbabilityInfo.h(2.69 KB)
📄 MachineCombinerPattern.h(3.5 KB)
📄 MachineConstantPool.h(5.25 KB)
📄 MachineDominanceFrontier.h(2.93 KB)
📄 MachineDominators.h(9.59 KB)
📄 MachineFrameInfo.h(34.84 KB)
📄 MachineFunction.h(42.94 KB)
📄 MachineFunctionPass.h(2.93 KB)
📄 MachineInstr.h(73.72 KB)
📄 MachineInstrBuilder.h(22.84 KB)
📄 MachineInstrBundle.h(10.16 KB)
📄 MachineInstrBundleIterator.h(10.92 KB)
📄 MachineJumpTableInfo.h(4.66 KB)
📄 MachineLoopInfo.h(7.3 KB)
📄 MachineLoopUtils.h(1.74 KB)
📄 MachineMemOperand.h(12.69 KB)
📄 MachineModuleInfo.h(9.88 KB)
📄 MachineModuleInfoImpls.h(3.36 KB)
📄 MachineOperand.h(37.64 KB)
📄 MachineOptimizationRemarkEmitter.h(8.99 KB)
📄 MachineOutliner.h(8.04 KB)
📄 MachinePassRegistry.h(6.1 KB)
📄 MachinePipeliner.h(21.17 KB)
📄 MachinePostDominators.h(2.93 KB)
📄 MachineRegionInfo.h(5.93 KB)
📄 MachineRegisterInfo.h(46.75 KB)
📄 MachineSSAUpdater.h(4.37 KB)
📄 MachineScheduler.h(36.6 KB)
📄 MachineSizeOpts.h(1.86 KB)
📄 MachineTraceMetrics.h(17.17 KB)
📄 MacroFusion.h(1.96 KB)
📄 ModuloSchedule.h(15.8 KB)
📄 NonRelocatableStringpool.h(2.9 KB)
📁 PBQP
📄 PBQPRAConstraint.h(1.83 KB)
📄 ParallelCG.h(1.66 KB)
📄 Passes.h(18.96 KB)
📄 PreISelIntrinsicLowering.h(944 B)
📄 PseudoSourceValue.h(6.21 KB)
📄 RDFGraph.h(33.73 KB)
📄 RDFLiveness.h(5.01 KB)
📄 RDFRegisters.h(6.51 KB)
📄 ReachingDefAnalysis.h(10.68 KB)
📄 RegAllocPBQP.h(16.47 KB)
📄 RegAllocRegistry.h(2.27 KB)
📄 Register.h(5.61 KB)
📄 RegisterClassInfo.h(4.86 KB)
📄 RegisterPressure.h(21.04 KB)
📄 RegisterScavenging.h(8.73 KB)
📄 RegisterUsageInfo.h(2.3 KB)
📄 ResourcePriorityQueue.h(4.19 KB)
📄 RuntimeLibcalls.h(3.05 KB)
📄 SDNodeProperties.td(1.57 KB)
📄 ScheduleDAG.h(28.92 KB)
📄 ScheduleDAGInstrs.h(15.49 KB)
📄 ScheduleDAGMutation.h(1021 B)
📄 ScheduleDFS.h(5.79 KB)
📄 ScheduleHazardRecognizer.h(4.65 KB)
📄 SchedulerRegistry.h(4.27 KB)
📄 ScoreboardHazardRecognizer.h(3.7 KB)
📄 SelectionDAG.h(89.12 KB)
📄 SelectionDAGAddressAnalysis.h(3.58 KB)
📄 SelectionDAGISel.h(13.48 KB)
📄 SelectionDAGNodes.h(91.77 KB)
📄 SelectionDAGTargetInfo.h(7.99 KB)
📄 SlotIndexes.h(24.12 KB)
📄 Spiller.h(1.16 KB)
📄 StackMaps.h(11.45 KB)
📄 StackProtector.h(4.1 KB)
📄 SwiftErrorValueTracking.h(3.87 KB)
📄 SwitchLoweringUtils.h(9.51 KB)
📄 TailDuplicator.h(5.54 KB)
📄 TargetCallingConv.h(8.26 KB)
📄 TargetFrameLowering.h(19.21 KB)
📄 TargetInstrInfo.h(84.48 KB)
📄 TargetLowering.h(194.17 KB)
📄 TargetLoweringObjectFileImpl.h(11.63 KB)
📄 TargetOpcodes.h(1.37 KB)
📄 TargetPassConfig.h(17.9 KB)
📄 TargetRegisterInfo.h(48.65 KB)
📄 TargetSchedule.h(7.75 KB)
📄 TargetSubtargetInfo.h(12.53 KB)
📄 UnreachableBlockElim.h(1.39 KB)
📄 ValueTypes.h(17.2 KB)
📄 ValueTypes.td(11.42 KB)
📄 VirtRegMap.h(6.37 KB)
📄 WasmEHFuncInfo.h(1.92 KB)
📄 WinEHFuncInfo.h(4.01 KB)

Editing: StackMaps.h

//===- StackMaps.h - StackMaps ----------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_STACKMAPS_H
#define LLVM_CODEGEN_STACKMAPS_H

#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/Debug.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <vector>

namespace llvm {

class AsmPrinter;
class MCExpr;
class MCStreamer;
class raw_ostream;
class TargetRegisterInfo;

/// MI-level stackmap operands.
///
/// MI stackmap operations take the form:
/// <id>, <numBytes>, live args...
class StackMapOpers {
public:
  /// Enumerate the meta operands.
  enum { IDPos, NBytesPos };

private:
  const MachineInstr* MI;

public:
  explicit StackMapOpers(const MachineInstr *MI);

/// Return the ID for the given stackmap
  uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }

/// Return the number of patchable bytes the given stackmap should emit.
  uint32_t getNumPatchBytes() const {
    return MI->getOperand(NBytesPos).getImm();
  }

/// Get the operand index of the variable list of non-argument operands.
  /// These hold the "live state".
  unsigned getVarIdx() const {
    // Skip ID, nShadowBytes.
    return 2;
  }
};

/// MI-level patchpoint operands.
///
/// MI patchpoint operations take the form:
/// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
///
/// IR patchpoint intrinsics do not have the <cc> operand because calling
/// convention is part of the subclass data.
///
/// SD patchpoint nodes do not have a def operand because it is part of the
/// SDValue.
///
/// Patchpoints following the anyregcc convention are handled specially. For
/// these, the stack map also records the location of the return value and
/// arguments.
class PatchPointOpers {
public:
  /// Enumerate the meta operands.
  enum { IDPos, NBytesPos, TargetPos, NArgPos, CCPos, MetaEnd };

private:
  const MachineInstr *MI;
  bool HasDef;

unsigned getMetaIdx(unsigned Pos = 0) const {
    assert(Pos < MetaEnd && "Meta operand index out of range.");
    return (HasDef ? 1 : 0) + Pos;
  }

const MachineOperand &getMetaOper(unsigned Pos) const {
    return MI->getOperand(getMetaIdx(Pos));
  }

public:
  explicit PatchPointOpers(const MachineInstr *MI);

bool isAnyReg() const { return (getCallingConv() == CallingConv::AnyReg); }
  bool hasDef() const { return HasDef; }

/// Return the ID for the given patchpoint.
  uint64_t getID() const { return getMetaOper(IDPos).getImm(); }

/// Return the number of patchable bytes the given patchpoint should emit.
  uint32_t getNumPatchBytes() const {
    return getMetaOper(NBytesPos).getImm();
  }

/// Returns the target of the underlying call.
  const MachineOperand &getCallTarget() const {
    return getMetaOper(TargetPos);
  }

/// Returns the calling convention
  CallingConv::ID getCallingConv() const {
    return getMetaOper(CCPos).getImm();
  }

unsigned getArgIdx() const { return getMetaIdx() + MetaEnd; }

/// Return the number of call arguments
  uint32_t getNumCallArgs() const {
    return MI->getOperand(getMetaIdx(NArgPos)).getImm();
  }

/// Get the operand index of the variable list of non-argument operands.
  /// These hold the "live state".
  unsigned getVarIdx() const {
    return getMetaIdx() + MetaEnd + getNumCallArgs();
  }

/// Get the index at which stack map locations will be recorded.
  /// Arguments are not recorded unless the anyregcc convention is used.
  unsigned getStackMapStartIdx() const {
    if (isAnyReg())
      return getArgIdx();
    return getVarIdx();
  }

/// Get the next scratch register operand index.
  unsigned getNextScratchIdx(unsigned StartIdx = 0) const;
};

/// MI-level Statepoint operands
///
/// Statepoint operands take the form:
///   <id>, <num patch bytes >, <num call arguments>, <call target>,
///   [call arguments...],
///   <StackMaps::ConstantOp>, <calling convention>,
///   <StackMaps::ConstantOp>, <statepoint flags>,
///   <StackMaps::ConstantOp>, <num deopt args>, [deopt args...],
///   <gc base/derived pairs...> <gc allocas...>
/// Note that the last two sets of arguments are not currently length
///   prefixed.
class StatepointOpers {
  // TODO:: we should change the STATEPOINT representation so that CC and
  // Flags should be part of meta operands, with args and deopt operands, and
  // gc operands all prefixed by their length and a type code. This would be
  // much more consistent.

// These values are absolute offsets into the operands of the statepoint
  // instruction.
  enum { IDPos, NBytesPos, NCallArgsPos, CallTargetPos, MetaEnd };

// These values are relative offsets from the start of the statepoint meta
  // arguments (i.e. the end of the call arguments).
  enum { CCOffset = 1, FlagsOffset = 3, NumDeoptOperandsOffset = 5 };

public:
  explicit StatepointOpers(const MachineInstr *MI) : MI(MI) {}

/// Get index of statepoint ID operand.
  unsigned getIDPos() const { return IDPos; }

/// Get index of Num Patch Bytes operand.
  unsigned getNBytesPos() const { return NBytesPos; }

/// Get index of Num Call Arguments operand.
  unsigned getNCallArgsPos() const { return NCallArgsPos; }

/// Get starting index of non call related arguments
  /// (calling convention, statepoint flags, vm state and gc state).
  unsigned getVarIdx() const {
    return MI->getOperand(NCallArgsPos).getImm() + MetaEnd;
  }

/// Get index of Calling Convention operand.
  unsigned getCCIdx() const { return getVarIdx() + CCOffset; }

/// Get index of Flags operand.
  unsigned getFlagsIdx() const { return getVarIdx() + FlagsOffset; }

/// Get index of Number Deopt Arguments operand.
  unsigned getNumDeoptArgsIdx() const {
    return getVarIdx() + NumDeoptOperandsOffset;
  }

/// Return the ID for the given statepoint.
  uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }

/// Return the number of patchable bytes the given statepoint should emit.
  uint32_t getNumPatchBytes() const {
    return MI->getOperand(NBytesPos).getImm();
  }

/// Return the target of the underlying call.
  const MachineOperand &getCallTarget() const {
    return MI->getOperand(CallTargetPos);
  }

/// Return the calling convention.
  CallingConv::ID getCallingConv() const {
    return MI->getOperand(getCCIdx()).getImm();
  }

/// Return the statepoint flags.
  uint64_t getFlags() const { return MI->getOperand(getFlagsIdx()).getImm(); }

private:
  const MachineInstr *MI;
};

class StackMaps {
public:
  struct Location {
    enum LocationType {
      Unprocessed,
      Register,
      Direct,
      Indirect,
      Constant,
      ConstantIndex
    };
    LocationType Type = Unprocessed;
    unsigned Size = 0;
    unsigned Reg = 0;
    int64_t Offset = 0;

Location() = default;
    Location(LocationType Type, unsigned Size, unsigned Reg, int64_t Offset)
        : Type(Type), Size(Size), Reg(Reg), Offset(Offset) {}
  };

struct LiveOutReg {
    unsigned short Reg = 0;
    unsigned short DwarfRegNum = 0;
    unsigned short Size = 0;

LiveOutReg() = default;
    LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum,
               unsigned short Size)
        : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {}
  };

// OpTypes are used to encode information about the following logical
  // operand (which may consist of several MachineOperands) for the
  // OpParser.
  using OpType = enum { DirectMemRefOp, IndirectMemRefOp, ConstantOp };

StackMaps(AsmPrinter &AP);

void reset() {
    CSInfos.clear();
    ConstPool.clear();
    FnInfos.clear();
  }

using LocationVec = SmallVector<Location, 8>;
  using LiveOutVec = SmallVector<LiveOutReg, 8>;
  using ConstantPool = MapVector<uint64_t, uint64_t>;

struct FunctionInfo {
    uint64_t StackSize = 0;
    uint64_t RecordCount = 1;

FunctionInfo() = default;
    explicit FunctionInfo(uint64_t StackSize) : StackSize(StackSize) {}
  };

struct CallsiteInfo {
    const MCExpr *CSOffsetExpr = nullptr;
    uint64_t ID = 0;
    LocationVec Locations;
    LiveOutVec LiveOuts;

CallsiteInfo() = default;
    CallsiteInfo(const MCExpr *CSOffsetExpr, uint64_t ID,
                 LocationVec &&Locations, LiveOutVec &&LiveOuts)
        : CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(std::move(Locations)),
          LiveOuts(std::move(LiveOuts)) {}
  };

using FnInfoMap = MapVector<const MCSymbol *, FunctionInfo>;
  using CallsiteInfoList = std::vector<CallsiteInfo>;

/// Generate a stackmap record for a stackmap instruction.
  ///
  /// MI must be a raw STACKMAP, not a PATCHPOINT.
  void recordStackMap(const MCSymbol &L,
                      const MachineInstr &MI);

/// Generate a stackmap record for a patchpoint instruction.
  void recordPatchPoint(const MCSymbol &L,
                        const MachineInstr &MI);

/// Generate a stackmap record for a statepoint instruction.
  void recordStatepoint(const MCSymbol &L,
                        const MachineInstr &MI);

/// If there is any stack map data, create a stack map section and serialize
  /// the map info into it. This clears the stack map data structures
  /// afterwards.
  void serializeToStackMapSection();

/// Get call site info.
  CallsiteInfoList &getCSInfos() { return CSInfos; }

/// Get function info.
  FnInfoMap &getFnInfos() { return FnInfos; }

private:
  static const char *WSMP;

AsmPrinter &AP;
  CallsiteInfoList CSInfos;
  ConstantPool ConstPool;
  FnInfoMap FnInfos;

MachineInstr::const_mop_iterator
  parseOperand(MachineInstr::const_mop_iterator MOI,
               MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
               LiveOutVec &LiveOuts) const;

/// Create a live-out register record for the given register @p Reg.
  LiveOutReg createLiveOutReg(unsigned Reg,
                              const TargetRegisterInfo *TRI) const;

/// Parse the register live-out mask and return a vector of live-out
  /// registers that need to be recorded in the stackmap.
  LiveOutVec parseRegisterLiveOutMask(const uint32_t *Mask) const;

/// Record the locations of the operands of the provided instruction in a
  /// record keyed by the provided label.  For instructions w/AnyReg calling
  /// convention the return register is also recorded if requested.  For
  /// STACKMAP, and PATCHPOINT the label is expected to immediately *preceed*
  /// lowering of the MI to MCInsts.  For STATEPOINT, it expected to
  /// immediately *follow*.  It's not clear this difference was intentional,
  /// but it exists today.  
  void recordStackMapOpers(const MCSymbol &L,
                           const MachineInstr &MI, uint64_t ID,
                           MachineInstr::const_mop_iterator MOI,
                           MachineInstr::const_mop_iterator MOE,
                           bool recordResult = false);

/// Emit the stackmap header.
  void emitStackmapHeader(MCStreamer &OS);

/// Emit the function frame record for each function.
  void emitFunctionFrameRecords(MCStreamer &OS);

/// Emit the constant pool.
  void emitConstantPoolEntries(MCStreamer &OS);

/// Emit the callsite info for each stackmap/patchpoint intrinsic call.
  void emitCallsiteEntries(MCStreamer &OS);

void print(raw_ostream &OS);
  void debug() { print(dbgs()); }
};

} // end namespace llvm

#endif // LLVM_CODEGEN_STACKMAPS_H

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