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Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/VE

usr / src / contrib / llvm-project / llvm / lib / Target / VE /

📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📁 TargetInfo
📄 VE.h(8.79 KB)
📄 VE.td(2.21 KB)
📄 VEAsmPrinter.cpp(12.54 KB)
📄 VECallingConv.td(3.05 KB)
📄 VEFrameLowering.cpp(13.39 KB)
📄 VEFrameLowering.h(3.35 KB)
📄 VEISelDAGToDAG.cpp(10.27 KB)
📄 VEISelLowering.cpp(37.14 KB)
📄 VEISelLowering.h(4.23 KB)
📄 VEInstrFormats.td(5.53 KB)
📄 VEInstrInfo.cpp(20.02 KB)
📄 VEInstrInfo.h(3.35 KB)
📄 VEInstrInfo.td(80.08 KB)
📄 VEMCInstLower.cpp(2.83 KB)
📄 VEMachineFunctionInfo.cpp(469 B)
📄 VEMachineFunctionInfo.h(1.57 KB)
📄 VERegisterInfo.cpp(5.07 KB)
📄 VERegisterInfo.h(1.75 KB)
📄 VERegisterInfo.td(5.67 KB)
📄 VESubtarget.cpp(4.04 KB)
📄 VESubtarget.h(2.38 KB)
📄 VETargetMachine.cpp(3.23 KB)
📄 VETargetMachine.h(1.95 KB)
📄 VETargetTransformInfo.h(1.72 KB)

Editing: VE.td

//===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===//
// VE Subtarget features.
//

//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
//===----------------------------------------------------------------------===//

include "VERegisterInfo.td"
include "VECallingConv.td"
include "VEInstrInfo.td"

def VEInstrInfo : InstrInfo;

def VEAsmParser : AsmParser {
  // Use both VE register name matcher to accept "S0~S63" register names
  // and default register matcher to accept other registeres.
  let AllowDuplicateRegisterNames = 1;
  let ShouldEmitMatchRegisterAltName = 1;
}

//===----------------------------------------------------------------------===//
// VE processors supported.
//===----------------------------------------------------------------------===//

class Proc<string Name, list<SubtargetFeature> Features>
 : Processor<Name, NoItineraries, Features>;

def : Proc<"ve",             []>;

//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//

def VEAsmWriter : AsmWriter {
  string AsmWriterClassName  = "InstPrinter";
  int PassSubtarget = 1;
  int Variant = 0;
}

def VE : Target {
  // Pull in Instruction Info:
  let InstructionSet = VEInstrInfo;
  let AssemblyParsers = [VEAsmParser];
  let AssemblyWriters = [VEAsmWriter];
  let AllowRegisterRenaming = 1;
}

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Editing: VE.td

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