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📁 ..
📄 AMDGPU.h(11.46 KB)
📄 AMDGPU.td(36.97 KB)
📄 AMDGPUAliasAnalysis.cpp(5.58 KB)
📄 AMDGPUAliasAnalysis.h(3.32 KB)
📄 AMDGPUAlwaysInlinePass.cpp(4.83 KB)
📄 AMDGPUAnnotateKernelFeatures.cpp(11.94 KB)
📄 AMDGPUAnnotateUniformValues.cpp(6.13 KB)
📄 AMDGPUArgumentUsageInfo.cpp(7.66 KB)
📄 AMDGPUArgumentUsageInfo.h(4.81 KB)
📄 AMDGPUAsmPrinter.cpp(50.42 KB)
📄 AMDGPUAsmPrinter.h(5.13 KB)
📄 AMDGPUAtomicOptimizer.cpp(23.79 KB)
📄 AMDGPUCallLowering.cpp(28.66 KB)
📄 AMDGPUCallLowering.h(2.37 KB)
📄 AMDGPUCallingConv.td(7.33 KB)
📄 AMDGPUCodeGenPrepare.cpp(46.42 KB)
📄 AMDGPUCombine.td(2.79 KB)
📄 AMDGPUExportClustering.cpp(4.52 KB)
📄 AMDGPUExportClustering.h(533 B)
📄 AMDGPUFeatures.td(1.81 KB)
📄 AMDGPUFixFunctionBitcasts.cpp(1.87 KB)
📄 AMDGPUFrameLowering.cpp(1.98 KB)
📄 AMDGPUFrameLowering.h(1.39 KB)
📄 AMDGPUGISel.td(11.57 KB)
📄 AMDGPUGenRegisterBankInfo.def(5.83 KB)
📄 AMDGPUGlobalISelUtils.cpp(1.77 KB)
📄 AMDGPUGlobalISelUtils.h(2.07 KB)
📄 AMDGPUHSAMetadataStreamer.cpp(31.21 KB)
📄 AMDGPUHSAMetadataStreamer.h(5.46 KB)
📄 AMDGPUISelDAGToDAG.cpp(101.59 KB)
📄 AMDGPUISelLowering.cpp(168.65 KB)
📄 AMDGPUISelLowering.h(19.23 KB)
📄 AMDGPUInline.cpp(7.97 KB)
📄 AMDGPUInstrInfo.cpp(1.71 KB)
📄 AMDGPUInstrInfo.h(1.66 KB)
📄 AMDGPUInstrInfo.td(17.18 KB)
📄 AMDGPUInstructionSelector.cpp(128.53 KB)
📄 AMDGPUInstructionSelector.h(11.04 KB)
📄 AMDGPUInstructions.td(25.36 KB)
📄 AMDGPULegalizerInfo.cpp(149.32 KB)
📄 AMDGPULegalizerInfo.h(8.49 KB)
📄 AMDGPULibCalls.cpp(53.89 KB)
📄 AMDGPULibFunc.cpp(37.85 KB)
📄 AMDGPULibFunc.h(10.99 KB)
📄 AMDGPULowerIntrinsics.cpp(4.55 KB)
📄 AMDGPULowerKernelArguments.cpp(8.89 KB)
📄 AMDGPULowerKernelAttributes.cpp(7.78 KB)
📄 AMDGPUMCInstLower.cpp(14.27 KB)
📄 AMDGPUMachineCFGStructurizer.cpp(101.97 KB)
📄 AMDGPUMachineFunction.cpp(2.24 KB)
📄 AMDGPUMachineFunction.h(2.13 KB)
📄 AMDGPUMachineModuleInfo.cpp(1.34 KB)
📄 AMDGPUMachineModuleInfo.h(5.46 KB)
📄 AMDGPUMacroFusion.cpp(2.28 KB)
📄 AMDGPUMacroFusion.h(679 B)
📄 AMDGPUOpenCLEnqueuedBlockLowering.cpp(5.31 KB)
📄 AMDGPUPTNote.h(1.29 KB)
📄 AMDGPUPerfHintAnalysis.cpp(12.17 KB)
📄 AMDGPUPerfHintAnalysis.h(1.67 KB)
📄 AMDGPUPostLegalizerCombiner.cpp(12.02 KB)
📄 AMDGPUPreLegalizerCombiner.cpp(5.45 KB)
📄 AMDGPUPrintfRuntimeBinding.cpp(21.7 KB)
📄 AMDGPUPromoteAlloca.cpp(35.24 KB)
📄 AMDGPUPropagateAttributes.cpp(11.76 KB)
📄 AMDGPURegBankCombiner.cpp(5.36 KB)
📄 AMDGPURegisterBankInfo.cpp(161.67 KB)
📄 AMDGPURegisterBankInfo.h(7.41 KB)
📄 AMDGPURegisterBanks.td(921 B)
📄 AMDGPURewriteOutArguments.cpp(15.82 KB)
📄 AMDGPUSearchableTables.td(21.04 KB)
📄 AMDGPUSubtarget.cpp(29.62 KB)
📄 AMDGPUSubtarget.h(35.82 KB)
📄 AMDGPUTargetMachine.cpp(42.67 KB)
📄 AMDGPUTargetMachine.h(4.52 KB)
📄 AMDGPUTargetObjectFile.cpp(1.54 KB)
📄 AMDGPUTargetObjectFile.h(1.14 KB)
📄 AMDGPUTargetTransformInfo.cpp(39.07 KB)
📄 AMDGPUTargetTransformInfo.h(11.11 KB)
📄 AMDGPUUnifyDivergentExitNodes.cpp(13.84 KB)
📄 AMDGPUUnifyMetadata.cpp(4.46 KB)
📄 AMDILCFGStructurizer.cpp(56.32 KB)
📄 AMDKernelCodeT.h(32.84 KB)
📁 AsmParser
📄 BUFInstructions.td(110.75 KB)
📄 CaymanInstructions.td(7.93 KB)
📄 DSInstructions.td(52.37 KB)
📁 Disassembler
📄 EvergreenInstructions.td(28.24 KB)
📄 FLATInstructions.td(66.93 KB)
📄 GCNDPPCombine.cpp(19.92 KB)
📄 GCNHazardRecognizer.cpp(45.3 KB)
📄 GCNHazardRecognizer.h(3.96 KB)
📄 GCNILPSched.cpp(11.3 KB)
📄 GCNIterativeScheduler.cpp(20.62 KB)
📄 GCNIterativeScheduler.h(4.16 KB)
📄 GCNMinRegStrategy.cpp(8.47 KB)
📄 GCNNSAReassign.cpp(10.92 KB)
📄 GCNProcessors.td(4.84 KB)
📄 GCNRegBankReassign.cpp(26.68 KB)
📄 GCNRegPressure.cpp(16.27 KB)
📄 GCNRegPressure.h(9.15 KB)
📄 GCNSchedStrategy.cpp(21.67 KB)
📄 GCNSchedStrategy.h(3.77 KB)
📁 MCTargetDesc
📄 MIMGInstructions.td(39.85 KB)
📄 R600.td(1.51 KB)
📄 R600AsmPrinter.cpp(4.46 KB)
📄 R600AsmPrinter.h(1.5 KB)
📄 R600ClauseMergePass.cpp(7.38 KB)
📄 R600ControlFlowFinalizer.cpp(23.4 KB)
📄 R600Defines.h(4.25 KB)
📄 R600EmitClauseMarkers.cpp(12.1 KB)
📄 R600ExpandSpecialInstrs.cpp(10.11 KB)
📄 R600FrameLowering.cpp(1.83 KB)
📄 R600FrameLowering.h(1.25 KB)
📄 R600ISelLowering.cpp(81.88 KB)
📄 R600ISelLowering.h(4.8 KB)
📄 R600InstrFormats.td(11.58 KB)
📄 R600InstrInfo.cpp(49.47 KB)
📄 R600InstrInfo.h(13.7 KB)
📄 R600Instructions.td(55.13 KB)
📄 R600MachineFunctionInfo.cpp(551 B)
📄 R600MachineFunctionInfo.h(824 B)
📄 R600MachineScheduler.cpp(13.57 KB)
📄 R600MachineScheduler.h(2.53 KB)
📄 R600OpenCLImageTypeLoweringPass.cpp(11.75 KB)
📄 R600OptimizeVectorRegisters.cpp(13.4 KB)
📄 R600Packetizer.cpp(13.4 KB)
📄 R600Processors.td(4.42 KB)
📄 R600RegisterInfo.cpp(3.95 KB)
📄 R600RegisterInfo.h(2 KB)
📄 R600RegisterInfo.td(9.75 KB)
📄 R600Schedule.td(1.62 KB)
📄 R700Instructions.td(783 B)
📄 SIAddIMGInit.cpp(6.24 KB)
📄 SIAnnotateControlFlow.cpp(11.18 KB)
📄 SIDefines.h(20.86 KB)
📄 SIFixSGPRCopies.cpp(29.46 KB)
📄 SIFixVGPRCopies.cpp(2 KB)
📄 SIFixupVectorISel.cpp(8.75 KB)
📄 SIFoldOperands.cpp(54.56 KB)
📄 SIFormMemoryClauses.cpp(12.76 KB)
📄 SIFrameLowering.cpp(48.08 KB)
📄 SIFrameLowering.h(2.98 KB)
📄 SIISelLowering.cpp(423.43 KB)
📄 SIISelLowering.h(22.13 KB)
📄 SIInsertHardClauses.cpp(7.01 KB)
📄 SIInsertSkips.cpp(15.29 KB)
📄 SIInsertWaitcnts.cpp(58.33 KB)
📄 SIInstrFormats.td(9.44 KB)
📄 SIInstrInfo.cpp(247.15 KB)
📄 SIInstrInfo.h(41.24 KB)
📄 SIInstrInfo.td(90.7 KB)
📄 SIInstructions.td(77.7 KB)
📄 SILoadStoreOptimizer.cpp(76.21 KB)
📄 SILowerControlFlow.cpp(22.66 KB)
📄 SILowerI1Copies.cpp(27.83 KB)
📄 SILowerSGPRSpills.cpp(12.68 KB)
📄 SIMachineFunctionInfo.cpp(20.01 KB)
📄 SIMachineFunctionInfo.h(26.91 KB)
📄 SIMachineScheduler.cpp(69.44 KB)
📄 SIMachineScheduler.h(15.65 KB)
📄 SIMemoryLegalizer.cpp(45.84 KB)
📄 SIModeRegister.cpp(17.43 KB)
📄 SIOptimizeExecMasking.cpp(12.81 KB)
📄 SIOptimizeExecMaskingPreRA.cpp(11.13 KB)
📄 SIPeepholeSDWA.cpp(42.84 KB)
📄 SIPostRABundler.cpp(3.6 KB)
📄 SIPreAllocateWWMRegs.cpp(6.09 KB)
📄 SIPreEmitPeephole.cpp(10.51 KB)
📄 SIProgramInfo.h(2.04 KB)
📄 SIRegisterInfo.cpp(71.51 KB)
📄 SIRegisterInfo.h(13.04 KB)
📄 SIRegisterInfo.td(37.28 KB)
📄 SIRemoveShortExecBranches.cpp(4.96 KB)
📄 SISchedule.td(7.58 KB)
📄 SIShrinkInstructions.cpp(26.86 KB)
📄 SIWholeQuadMode.cpp(30.22 KB)
📄 SMInstructions.td(48.14 KB)
📄 SOPInstructions.td(60.51 KB)
📁 TargetInfo
📁 Utils
📄 VIInstrFormats.td(645 B)
📄 VOP1Instructions.td(35.53 KB)
📄 VOP2Instructions.td(65.04 KB)
📄 VOP3Instructions.td(53.14 KB)
📄 VOP3PInstructions.td(26.47 KB)
📄 VOPCInstructions.td(63.31 KB)
📄 VOPInstructions.td(23.76 KB)

Editing: VOPCInstructions.td

//===-- VOPCInstructions.td - Vector Instruction Definitions --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Encodings
//===----------------------------------------------------------------------===//

class VOPCe <bits<8> op> : Enc32 {
  bits<9> src0;
  bits<8> src1;

let Inst{8-0} = src0;
  let Inst{16-9} = src1;
  let Inst{24-17} = op;
  let Inst{31-25} = 0x3e;
}

class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
  bits<8> src1;

let Inst{8-0}   = 0xf9; // sdwa
  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
  let Inst{24-17} = op;
  let Inst{31-25} = 0x3e; // encoding

// VOPC disallows dst_sel and dst_unused as they have no effect on destination
  let Inst{42-40} = 0;
  let Inst{44-43} = 0;
}

class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
  bits<9> src1;

let Inst{8-0}   = 0xf9; // sdwa
  let Inst{16-9}  = !if(P.HasSrc1, src1{7-0}, 0);
  let Inst{24-17} = op;
  let Inst{31-25} = 0x3e; // encoding
  let Inst{63}    = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
}

//===----------------------------------------------------------------------===//
// VOPC classes
//===----------------------------------------------------------------------===//

// VOPC instructions are a special case because for the 32-bit
// encoding, we want to display the implicit vcc write as if it were
// an explicit $dst.
class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> :
  VOPProfile <[i1, vt0, vt1, untyped]> {
  let Asm32 = "$src0, $src1";
  // The destination for 32-bit encoding is implicit.
  let HasDst32 = 0;
  let Outs64 = (outs VOPDstS64orS32:$sdst);
  list<SchedReadWrite> Schedule = sched;
}

class VOPC_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt0,
                          ValueType vt1 = vt0> :
  VOPC_Profile<sched, vt0, vt1> {
  let Outs64 = (outs );
  let OutsSDWA = (outs );
  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
                     src0_sel:$src0_sel, src1_sel:$src1_sel);
  let Asm64 = !if(isFloatType<Src0VT>.ret, "$src0_modifiers, $src1_modifiers$clamp",
                                           "$src0, $src1");
  let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
  let EmitDst = 0;
}

class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],
                   bit DefVcc = 1> :
  InstSI<(outs), P.Ins32, "", pattern>,
  VOP <opName>,
  SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {

let isPseudo = 1;
  let isCodeGenOnly = 1;
  let UseNamedOperandTable = 1;

string Mnemonic = opName;
  string AsmOperands = P.Asm32;

let Size = 4;
  let mayLoad = 0;
  let mayStore = 0;
  let hasSideEffects = 0;

let ReadsModeReg = isFloatType<P.Src0VT>.ret;

let VALU = 1;
  let VOPC = 1;
  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);
  let Defs = !if(DefVcc, [VCC], []);

VOPProfile Pfl = P;
}

class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
  InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,
  SIMCInstr <ps.PseudoInstr, EncodingFamily> {

let isPseudo = 0;
  let isCodeGenOnly = 0;

let Constraints     = ps.Constraints;
  let DisableEncoding = ps.DisableEncoding;

// copy relevant pseudo op flags
  let SubtargetPredicate = ps.SubtargetPredicate;
  let AsmMatchConverter  = ps.AsmMatchConverter;
  let Constraints        = ps.Constraints;
  let DisableEncoding    = ps.DisableEncoding;
  let TSFlags            = ps.TSFlags;
  let UseNamedOperandTable = ps.UseNamedOperandTable;
  let Uses                 = ps.Uses;
  let Defs                 = ps.Defs;
}

class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
  VOP_SDWA_Pseudo <OpName, P, pattern> {
  let AsmMatchConverter = "cvtSdwaVOPC";
}

// This class is used only with VOPC instructions. Use $sdst for out operand
class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst,
                     string Asm32 = ps.Pfl.Asm32, VOPProfile p = ps.Pfl> :
  InstAlias <ps.OpName#" "#Asm32, (inst)>, PredicateControl {

field bit isCompare;
  field bit isCommutable;

let ResultInst =
    !if (p.HasDst32,
      !if (!eq(p.NumSrcArgs, 0),
        // 1 dst, 0 src
        (inst p.DstRC:$sdst),
      !if (!eq(p.NumSrcArgs, 1),
        // 1 dst, 1 src
        (inst p.DstRC:$sdst, p.Src0RC32:$src0),
      !if (!eq(p.NumSrcArgs, 2),
        // 1 dst, 2 src
        (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
      // else - unreachable
        (inst)))),
    // else
      !if (!eq(p.NumSrcArgs, 2),
        // 0 dst, 2 src
        (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
      !if (!eq(p.NumSrcArgs, 1),
        // 0 dst, 1 src
        (inst p.Src0RC32:$src1),
      // else
        // 0 dst, 0 src
        (inst))));

let AsmVariantName = AMDGPUAsmVariants.Default;
  let SubtargetPredicate = AssemblerPredicate;
}

multiclass VOPCInstAliases <string OpName, string Arch> {
  def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
                       !cast<Instruction>(OpName#"_e32_"#Arch)>;
  let WaveSizePredicate = isWave32 in {
    def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
                         !cast<Instruction>(OpName#"_e32_"#Arch),
                         "vcc_lo, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;
  }
  let WaveSizePredicate = isWave64 in {
    def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
                         !cast<Instruction>(OpName#"_e32_"#Arch),
                         "vcc, "#!cast<VOP3_Pseudo>(OpName#"_e64").Pfl.Asm32>;
  }
}

multiclass VOPCXInstAliases <string OpName, string Arch> {
  def : VOPCInstAlias <!cast<VOP3_Pseudo>(OpName#"_e64"),
                       !cast<Instruction>(OpName#"_e32_"#Arch)>;
}

class getVOPCPat64 <SDPatternOperator cond, VOPProfile P> : LetDummies {
  list<dag> ret = !if(P.HasModifiers,
      [(set i1:$sdst,
        (setcc (P.Src0VT
                  !if(P.HasOMod,
                    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
                    (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
               (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
               cond))],
      [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);
}

class VCMPXNoSDstTable <bit has_sdst, string Name> {
  bit HasSDst = has_sdst;
  string NoSDstOp = Name;
}

multiclass VOPC_Pseudos <string opName,
                         VOPC_Profile P,
                         SDPatternOperator cond = COND_NULL,
                         string revOp = opName,
                         bit DefExec = 0> {

def _e32 : VOPC_Pseudo <opName, P>,
             Commutable_REV<revOp#"_e32", !eq(revOp, opName)>,
             VCMPXNoSDstTable<1, opName#"_e32"> {
    let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
    let SchedRW = P.Schedule;
    let isConvergent = DefExec;
    let isCompare = 1;
    let isCommutable = 1;
  }

def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>,
    Commutable_REV<revOp#"_e64", !eq(revOp, opName)>,
    VCMPXNoSDstTable<1, opName#"_e64"> {
    let Defs = !if(DefExec, [EXEC], []);
    let SchedRW = P.Schedule;
    let isCompare = 1;
    let isCommutable = 1;
  }

foreach _ = BoolToList<P.HasExtSDWA>.ret in
  def _sdwa : VOPC_SDWA_Pseudo <opName, P> {
    let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
    let SchedRW = P.Schedule;
    let isConvergent = DefExec;
    let isCompare = 1;
  }
}

let SubtargetPredicate = HasSdstCMPX in {
multiclass VOPCX_Pseudos <string opName,
                          VOPC_Profile P, VOPC_Profile P_NoSDst,
                          SDPatternOperator cond = COND_NULL,
                          string revOp = opName> :
           VOPC_Pseudos <opName, P, cond, revOp, 1> {

def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>,
             Commutable_REV<revOp#"_nosdst_e32", !eq(revOp, opName)>,
             VCMPXNoSDstTable<0, opName#"_e32"> {
    let Defs = [EXEC];
    let SchedRW = P_NoSDst.Schedule;
    let isConvergent = 1;
    let isCompare = 1;
    let isCommutable = 1;
    let SubtargetPredicate = HasNoSdstCMPX;
  }

def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
    Commutable_REV<revOp#"_nosdst_e64", !eq(revOp, opName)>,
    VCMPXNoSDstTable<0, opName#"_e64"> {
    let Defs = [EXEC];
    let SchedRW = P_NoSDst.Schedule;
    let isCompare = 1;
    let isCommutable = 1;
    let SubtargetPredicate = HasNoSdstCMPX;
  }

foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
  def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> {
    let Defs = [EXEC];
    let SchedRW = P_NoSDst.Schedule;
    let isConvergent = 1;
    let isCompare = 1;
    let SubtargetPredicate = HasNoSdstCMPX;
  }
}
} // End SubtargetPredicate = HasSdstCMPX

def VOPC_I1_F16_F16 : VOPC_Profile<[Write32Bit], f16>;
def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>;
def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>;
def VOPC_I1_I16_I16 : VOPC_Profile<[Write32Bit], i16>;
def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>;
def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>;

def VOPC_F16_F16 : VOPC_NoSdst_Profile<[Write32Bit], f16>;
def VOPC_F32_F32 : VOPC_NoSdst_Profile<[Write32Bit], f32>;
def VOPC_F64_F64 : VOPC_NoSdst_Profile<[Write64Bit], f64>;
def VOPC_I16_I16 : VOPC_NoSdst_Profile<[Write32Bit], i16>;
def VOPC_I32_I32 : VOPC_NoSdst_Profile<[Write32Bit], i32>;
def VOPC_I64_I64 : VOPC_NoSdst_Profile<[Write64Bit], i64>;

multiclass VOPC_F16 <string opName, SDPatternOperator cond = COND_NULL,
                     string revOp = opName> :
  VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>;

multiclass VOPC_F32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
  VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>;

multiclass VOPC_F64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
  VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>;

multiclass VOPC_I16 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
  VOPC_Pseudos <opName, VOPC_I1_I16_I16, cond, revOp, 0>;

multiclass VOPC_I32 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
  VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>;

multiclass VOPC_I64 <string opName, SDPatternOperator cond = COND_NULL, string revOp = opName> :
  VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>;

multiclass VOPCX_F16 <string opName, string revOp = opName> :
  VOPCX_Pseudos <opName, VOPC_I1_F16_F16, VOPC_F16_F16, COND_NULL, revOp>;

multiclass VOPCX_F32 <string opName, string revOp = opName> :
  VOPCX_Pseudos <opName, VOPC_I1_F32_F32, VOPC_F32_F32, COND_NULL, revOp>;

multiclass VOPCX_F64 <string opName, string revOp = opName> :
  VOPCX_Pseudos <opName, VOPC_I1_F64_F64, VOPC_F64_F64, COND_NULL, revOp>;

multiclass VOPCX_I16 <string opName, string revOp = opName> :
  VOPCX_Pseudos <opName, VOPC_I1_I16_I16, VOPC_I16_I16, COND_NULL, revOp>;

multiclass VOPCX_I32 <string opName, string revOp = opName> :
  VOPCX_Pseudos <opName, VOPC_I1_I32_I32, VOPC_I32_I32, COND_NULL, revOp>;

multiclass VOPCX_I64 <string opName, string revOp = opName> :
  VOPCX_Pseudos <opName, VOPC_I1_I64_I64, VOPC_I64_I64, COND_NULL, revOp>;

//===----------------------------------------------------------------------===//
// Compare instructions
//===----------------------------------------------------------------------===//

defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">;
defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>;
defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">;
defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>;
defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>;
defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>;
defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>;
defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>;
defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32",  COND_ULT, "v_cmp_nle_f32">;
defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>;
defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">;
defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>;
defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>;
defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>;
defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">;

defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">;
defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">;
defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">;
defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">;
defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">;
defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">;
defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">;
defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">;
defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">;
defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">;
defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">;
defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">;
defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">;
defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">;
defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">;
defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">;

defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">;
defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">;
defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>;
defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">;
defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>;
defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>;
defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>;
defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>;
defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>;
defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">;
defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>;
defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">;
defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>;
defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>;
defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>;
defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">;

defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">;
defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">;
defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">;
defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">;
defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">;
defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">;
defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">;
defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">;
defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">;
defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">;
defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">;
defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">;
defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">;
defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">;
defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">;
defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">;

let SubtargetPredicate = isGFX6GFX7 in {

defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">;
defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">;
defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">;
defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">;
defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">;
defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">;
defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">;
defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">;
defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">;
defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">;
defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">;
defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">;
defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">;
defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">;
defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">;
defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">;

defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">;
defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">;
defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">;
defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">;
defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">;
defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">;
defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">;
defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">;
defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">;
defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">;
defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">;
defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">;
defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">;
defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">;
defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">;
defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">;

defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">;
defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">;
defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">;
defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">;
defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">;
defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">;
defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">;
defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">;
defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">;
defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">;
defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">;
defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">;
defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">;
defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">;
defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">;
defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">;

defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">;
defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">;
defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">;
defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">;
defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">;
defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">;
defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">;
defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">;
defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">;
defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">;
defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">;
defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">;
defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">;
defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">;
defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">;
defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">;

} // End SubtargetPredicate = isGFX6GFX7

let SubtargetPredicate = Has16BitInsts in {

defm V_CMP_F_F16    : VOPC_F16 <"v_cmp_f_f16">;
defm V_CMP_LT_F16   : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">;
defm V_CMP_EQ_F16   : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>;
defm V_CMP_LE_F16   : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">;
defm V_CMP_GT_F16   : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>;
defm V_CMP_LG_F16   : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>;
defm V_CMP_GE_F16   : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>;
defm V_CMP_O_F16    : VOPC_F16 <"v_cmp_o_f16", COND_O>;
defm V_CMP_U_F16    : VOPC_F16 <"v_cmp_u_f16", COND_UO>;
defm V_CMP_NGE_F16  : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">;
defm V_CMP_NLG_F16  : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>;
defm V_CMP_NGT_F16  : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">;
defm V_CMP_NLE_F16  : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>;
defm V_CMP_NEQ_F16  : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>;
defm V_CMP_NLT_F16  : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>;
defm V_CMP_TRU_F16  : VOPC_F16 <"v_cmp_tru_f16">;

defm V_CMPX_F_F16   : VOPCX_F16 <"v_cmpx_f_f16">;
defm V_CMPX_LT_F16  : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">;
defm V_CMPX_EQ_F16  : VOPCX_F16 <"v_cmpx_eq_f16">;
defm V_CMPX_LE_F16  : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">;
defm V_CMPX_GT_F16  : VOPCX_F16 <"v_cmpx_gt_f16">;
defm V_CMPX_LG_F16  : VOPCX_F16 <"v_cmpx_lg_f16">;
defm V_CMPX_GE_F16  : VOPCX_F16 <"v_cmpx_ge_f16">;
defm V_CMPX_O_F16   : VOPCX_F16 <"v_cmpx_o_f16">;
defm V_CMPX_U_F16   : VOPCX_F16 <"v_cmpx_u_f16">;
defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">;
defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">;
defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">;
defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">;
defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">;
defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">;
defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">;

defm V_CMP_F_I16 : VOPC_I16 <"v_cmp_f_i16">;
defm V_CMP_LT_I16 : VOPC_I16 <"v_cmp_lt_i16", COND_SLT, "v_cmp_gt_i16">;
defm V_CMP_EQ_I16 : VOPC_I16 <"v_cmp_eq_i16">;
defm V_CMP_LE_I16 : VOPC_I16 <"v_cmp_le_i16", COND_SLE, "v_cmp_ge_i16">;
defm V_CMP_GT_I16 : VOPC_I16 <"v_cmp_gt_i16", COND_SGT>;
defm V_CMP_NE_I16 : VOPC_I16 <"v_cmp_ne_i16">;
defm V_CMP_GE_I16 : VOPC_I16 <"v_cmp_ge_i16", COND_SGE>;
defm V_CMP_T_I16 : VOPC_I16 <"v_cmp_t_i16">;

defm V_CMP_F_U16 : VOPC_I16 <"v_cmp_f_u16">;
defm V_CMP_LT_U16 : VOPC_I16 <"v_cmp_lt_u16", COND_ULT, "v_cmp_gt_u16">;
defm V_CMP_EQ_U16 : VOPC_I16 <"v_cmp_eq_u16", COND_EQ>;
defm V_CMP_LE_U16 : VOPC_I16 <"v_cmp_le_u16", COND_ULE, "v_cmp_ge_u16">;
defm V_CMP_GT_U16 : VOPC_I16 <"v_cmp_gt_u16", COND_UGT>;
defm V_CMP_NE_U16 : VOPC_I16 <"v_cmp_ne_u16", COND_NE>;
defm V_CMP_GE_U16 : VOPC_I16 <"v_cmp_ge_u16", COND_UGE>;
defm V_CMP_T_U16 : VOPC_I16 <"v_cmp_t_u16">;

defm V_CMPX_F_I16 : VOPCX_I16 <"v_cmpx_f_i16">;
defm V_CMPX_LT_I16 : VOPCX_I16 <"v_cmpx_lt_i16", "v_cmpx_gt_i16">;
defm V_CMPX_EQ_I16 : VOPCX_I16 <"v_cmpx_eq_i16">;
defm V_CMPX_LE_I16 : VOPCX_I16 <"v_cmpx_le_i16", "v_cmpx_ge_i16">;
defm V_CMPX_GT_I16 : VOPCX_I16 <"v_cmpx_gt_i16">;
defm V_CMPX_NE_I16 : VOPCX_I16 <"v_cmpx_ne_i16">;
defm V_CMPX_GE_I16 : VOPCX_I16 <"v_cmpx_ge_i16">;
defm V_CMPX_T_I16 : VOPCX_I16 <"v_cmpx_t_i16">;
defm V_CMPX_F_U16 : VOPCX_I16 <"v_cmpx_f_u16">;

defm V_CMPX_LT_U16 : VOPCX_I16 <"v_cmpx_lt_u16", "v_cmpx_gt_u16">;
defm V_CMPX_EQ_U16 : VOPCX_I16 <"v_cmpx_eq_u16">;
defm V_CMPX_LE_U16 : VOPCX_I16 <"v_cmpx_le_u16", "v_cmpx_ge_u16">;
defm V_CMPX_GT_U16 : VOPCX_I16 <"v_cmpx_gt_u16">;
defm V_CMPX_NE_U16 : VOPCX_I16 <"v_cmpx_ne_u16">;
defm V_CMPX_GE_U16 : VOPCX_I16 <"v_cmpx_ge_u16">;
defm V_CMPX_T_U16 : VOPCX_I16 <"v_cmpx_t_u16">;

} // End SubtargetPredicate = Has16BitInsts

defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">;
defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">;
defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">;
defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">;
defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>;
defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">;
defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>;
defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">;

defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">;
defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">;
defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">;
defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">;
defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">;
defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">;
defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">;
defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">;

defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">;
defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">;
defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">;
defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">;
defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>;
defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">;
defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>;
defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">;

defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">;
defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">;
defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">;
defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">;
defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">;
defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">;
defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">;
defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">;

defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">;
defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">;
defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>;
defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">;
defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>;
defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>;
defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>;
defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">;

defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">;
defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">;
defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">;
defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">;
defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">;
defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">;
defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">;
defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">;

defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">;
defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">;
defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>;
defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">;
defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>;
defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>;
defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>;
defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">;

defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">;
defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">;
defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">;
defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">;
defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">;
defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">;
defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">;
defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">;

//===----------------------------------------------------------------------===//
// Class instructions
//===----------------------------------------------------------------------===//

class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> :
  VOPC_Profile<sched, vt, i32> {
  let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
  let Asm64 = "$sdst, $src0_modifiers, $src1";

let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
                     clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel);

let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel";
  let HasSrc1Mods = 0;
  let HasClamp = 0;
  let HasOMod = 0;
}

class VOPC_Class_NoSdst_Profile<list<SchedReadWrite> sched, ValueType vt> :
  VOPC_Class_Profile<sched, vt> {
  let Outs64 = (outs );
  let OutsSDWA = (outs );
  let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
                     Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
                     src0_sel:$src0_sel, src1_sel:$src1_sel);
  let Asm64 = "$src0_modifiers, $src1";
  let AsmSDWA9 = "$src0_modifiers, $src1_modifiers $src0_sel $src1_sel";
  let EmitDst = 0;
}

class getVOPCClassPat64 <VOPProfile P> {
  list<dag> ret =
    [(set i1:$sdst,
      (AMDGPUfp_class
        (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers)),
        P.Src1VT:$src1))];
}

// Special case for class instructions which only have modifiers on
// the 1st source operand.
multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec,
                               bit DefVcc = 1> {
  def _e32 : VOPC_Pseudo <opName, p>,
             VCMPXNoSDstTable<1, opName#"_e32"> {
    let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
                            !if(DefVcc, [VCC], []));
    let SchedRW = p.Schedule;
    let isConvergent = DefExec;
  }

def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>,
             VCMPXNoSDstTable<1, opName#"_e64"> {
    let Defs = !if(DefExec, [EXEC], []);
    let SchedRW = p.Schedule;
  }

foreach _ = BoolToList<p.HasExtSDWA>.ret in
  def _sdwa : VOPC_SDWA_Pseudo <opName, p> {
    let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
                            !if(DefVcc, [VCC], []));
    let SchedRW = p.Schedule;
    let isConvergent = DefExec;
  }
}

let SubtargetPredicate = HasSdstCMPX in {
multiclass VOPCX_Class_Pseudos <string opName,
                                VOPC_Profile P,
                                VOPC_Profile P_NoSDst> :
           VOPC_Class_Pseudos <opName, P, 1, 1> {

def _nosdst_e32 : VOPC_Pseudo <opName#"_nosdst", P_NoSDst, [], 0>,
                    VCMPXNoSDstTable<0, opName#"_e32"> {
    let Defs = [EXEC];
    let SchedRW = P_NoSDst.Schedule;
    let isConvergent = 1;
    let SubtargetPredicate = HasNoSdstCMPX;
  }

def _nosdst_e64 : VOP3_Pseudo<opName#"_nosdst", P_NoSDst>,
                    VCMPXNoSDstTable<0, opName#"_e64"> {
    let Defs = [EXEC];
    let SchedRW = P_NoSDst.Schedule;
    let SubtargetPredicate = HasNoSdstCMPX;
  }

foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
  def _nosdst_sdwa : VOPC_SDWA_Pseudo <opName#"_nosdst", P_NoSDst> {
    let Defs = [EXEC];
    let SchedRW = P_NoSDst.Schedule;
    let isConvergent = 1;
    let SubtargetPredicate = HasNoSdstCMPX;
  }
}
} // End SubtargetPredicate = HasSdstCMPX

def VOPC_I1_F16_I32 : VOPC_Class_Profile<[Write32Bit], f16>;
def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>;
def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>;

def VOPC_F16_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f16>;
def VOPC_F32_I32 : VOPC_Class_NoSdst_Profile<[Write32Bit], f32>;
def VOPC_F64_I32 : VOPC_Class_NoSdst_Profile<[Write64Bit], f64>;

multiclass VOPC_CLASS_F16 <string opName> :
  VOPC_Class_Pseudos <opName, VOPC_I1_F16_I32, 0>;

multiclass VOPCX_CLASS_F16 <string opName> :
  VOPCX_Class_Pseudos <opName, VOPC_I1_F16_I32, VOPC_F16_I32>;

multiclass VOPC_CLASS_F32 <string opName> :
  VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>;

multiclass VOPCX_CLASS_F32 <string opName> :
  VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>;

multiclass VOPC_CLASS_F64 <string opName> :
  VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;

multiclass VOPCX_CLASS_F64 <string opName> :
  VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>;

// cmp_class ignores the FP mode and faithfully reports the unmodified
// source value.
let ReadsModeReg = 0, mayRaiseFPException = 0 in {
defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;

let SubtargetPredicate = Has16BitInsts in {
defm V_CMP_CLASS_F16  : VOPC_CLASS_F16 <"v_cmp_class_f16">;
defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
}
} // End ReadsModeReg = 0, mayRaiseFPException = 0

//===----------------------------------------------------------------------===//
// V_ICMPIntrinsic Pattern.
//===----------------------------------------------------------------------===//

// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()
// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.
multiclass ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {
  let WaveSizePredicate = isWave64 in
  def : GCNPat <
    (i64 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
    (i64 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_64))
  >;

let WaveSizePredicate = isWave32 in
  def : GCNPat <
    (i32 (AMDGPUsetcc vt:$src0, vt:$src1, cond)),
    (i32 (COPY_TO_REGCLASS (inst $src0, $src1), SReg_32))
  >;
}

defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>;
defm : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>;
defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>;
defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>;
defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>;
defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>;
defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>;
defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>;
defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>;
defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>;

defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>;
defm : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>;
defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>;
defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>;
defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>;
defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>;
defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>;
defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>;
defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;

defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>;
defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>;
defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>;
defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_e64, i16>;
defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_e64, i16>;
defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_e64, i16>;
defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_e64, i16>;
defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>;
defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>;
defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;

multiclass FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {
  let WaveSizePredicate = isWave64 in
  def : GCNPat <
    (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
                 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
    (i64 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
                           DSTCLAMP.NONE), SReg_64))
  >;

let WaveSizePredicate = isWave32 in
  def : GCNPat <
    (i32 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
                 (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),
    (i32 (COPY_TO_REGCLASS (inst $src0_modifiers, $src0, $src1_modifiers, $src1,
                           DSTCLAMP.NONE), SReg_32))
  >;
}

defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;
defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>;
defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>;
defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>;
defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>;
defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>;

defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>;
defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>;
defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>;
defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>;
defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;

defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>;
defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>;
defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>;
defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>;
defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>;
defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>;

defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>;
defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>;
defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;

defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;

defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>;
defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>;
defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>;
defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>;
defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>;
defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>;

//===----------------------------------------------------------------------===//
// Target-specific instruction encodings.
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// GFX10.
//===----------------------------------------------------------------------===//

foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
    def _sdwa_gfx10 :
      VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
      VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;

defm : VOPCInstAliases<NAME, "gfx10">;
  }

multiclass VOPCX_Real_gfx10<bits<9> op> {
    let DecoderNamespace = "GFX10" in {
      def _e32_gfx10 :
        VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32"), SIEncodingFamily.GFX10>,
        VOPCe<op{7-0}> {
          let AsmString = !subst("_nosdst", "", !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").PseudoInstr)
                          # " " # !cast<VOPC_Pseudo>(NAME#"_nosdst_e32").AsmOperands;
        }

def _e64_gfx10 :
        VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_nosdst_e64"), SIEncodingFamily.GFX10>,
        VOP3a_gfx10<{0, op}, !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Pfl> {
          let Inst{7-0} = ?; // sdst
          let AsmString = !subst("_nosdst", "", !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").Mnemonic)
                          # "{_e64} " # !cast<VOP3_Pseudo>(NAME#"_nosdst_e64").AsmOperands;
        }
    } // End DecoderNamespace = "GFX10"

foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_nosdst_e32").Pfl.HasExtSDWA9>.ret in
    def _sdwa_gfx10 :
      VOP_SDWA10_Real<!cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa")>,
      VOPC_SDWA9e<op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Pfl> {
        let AsmString = !subst("_nosdst", "", !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").Mnemonic)
                        # "{_sdwa} " # !cast<VOPC_SDWA_Pseudo>(NAME#"_nosdst_sdwa").AsmOperands9;
      }

defm : VOPCXInstAliases<NAME, "gfx10">;
  }
} // End AssemblerPredicate = isGFX10Plus

defm V_CMP_LT_I16     : VOPC_Real_gfx10<0x089>;
defm V_CMP_EQ_I16     : VOPC_Real_gfx10<0x08a>;
defm V_CMP_LE_I16     : VOPC_Real_gfx10<0x08b>;
defm V_CMP_GT_I16     : VOPC_Real_gfx10<0x08c>;
defm V_CMP_NE_I16     : VOPC_Real_gfx10<0x08d>;
defm V_CMP_GE_I16     : VOPC_Real_gfx10<0x08e>;
defm V_CMP_CLASS_F16  : VOPC_Real_gfx10<0x08f>;
defm V_CMPX_LT_I16    : VOPCX_Real_gfx10<0x099>;
defm V_CMPX_EQ_I16    : VOPCX_Real_gfx10<0x09a>;
defm V_CMPX_LE_I16    : VOPCX_Real_gfx10<0x09b>;
defm V_CMPX_GT_I16    : VOPCX_Real_gfx10<0x09c>;
defm V_CMPX_NE_I16    : VOPCX_Real_gfx10<0x09d>;
defm V_CMPX_GE_I16    : VOPCX_Real_gfx10<0x09e>;
defm V_CMPX_CLASS_F16 : VOPCX_Real_gfx10<0x09f>;
defm V_CMP_LT_U16     : VOPC_Real_gfx10<0x0a9>;
defm V_CMP_EQ_U16     : VOPC_Real_gfx10<0x0aa>;
defm V_CMP_LE_U16     : VOPC_Real_gfx10<0x0ab>;
defm V_CMP_GT_U16     : VOPC_Real_gfx10<0x0ac>;
defm V_CMP_NE_U16     : VOPC_Real_gfx10<0x0ad>;
defm V_CMP_GE_U16     : VOPC_Real_gfx10<0x0ae>;
defm V_CMPX_LT_U16    : VOPCX_Real_gfx10<0x0b9>;
defm V_CMPX_EQ_U16    : VOPCX_Real_gfx10<0x0ba>;
defm V_CMPX_LE_U16    : VOPCX_Real_gfx10<0x0bb>;
defm V_CMPX_GT_U16    : VOPCX_Real_gfx10<0x0bc>;
defm V_CMPX_NE_U16    : VOPCX_Real_gfx10<0x0bd>;
defm V_CMPX_GE_U16    : VOPCX_Real_gfx10<0x0be>;
defm V_CMP_F_F16      : VOPC_Real_gfx10<0x0c8>;
defm V_CMP_LT_F16     : VOPC_Real_gfx10<0x0c9>;
defm V_CMP_EQ_F16     : VOPC_Real_gfx10<0x0ca>;
defm V_CMP_LE_F16     : VOPC_Real_gfx10<0x0cb>;
defm V_CMP_GT_F16     : VOPC_Real_gfx10<0x0cc>;
defm V_CMP_LG_F16     : VOPC_Real_gfx10<0x0cd>;
defm V_CMP_GE_F16     : VOPC_Real_gfx10<0x0ce>;
defm V_CMP_O_F16      : VOPC_Real_gfx10<0x0cf>;
defm V_CMPX_F_F16     : VOPCX_Real_gfx10<0x0d8>;
defm V_CMPX_LT_F16    : VOPCX_Real_gfx10<0x0d9>;
defm V_CMPX_EQ_F16    : VOPCX_Real_gfx10<0x0da>;
defm V_CMPX_LE_F16    : VOPCX_Real_gfx10<0x0db>;
defm V_CMPX_GT_F16    : VOPCX_Real_gfx10<0x0dc>;
defm V_CMPX_LG_F16    : VOPCX_Real_gfx10<0x0dd>;
defm V_CMPX_GE_F16    : VOPCX_Real_gfx10<0x0de>;
defm V_CMPX_O_F16     : VOPCX_Real_gfx10<0x0df>;
defm V_CMP_U_F16      : VOPC_Real_gfx10<0x0e8>;
defm V_CMP_NGE_F16    : VOPC_Real_gfx10<0x0e9>;
defm V_CMP_NLG_F16    : VOPC_Real_gfx10<0x0ea>;
defm V_CMP_NGT_F16    : VOPC_Real_gfx10<0x0eb>;
defm V_CMP_NLE_F16    : VOPC_Real_gfx10<0x0ec>;
defm V_CMP_NEQ_F16    : VOPC_Real_gfx10<0x0ed>;
defm V_CMP_NLT_F16    : VOPC_Real_gfx10<0x0ee>;
defm V_CMP_TRU_F16    : VOPC_Real_gfx10<0x0ef>;
defm V_CMPX_U_F16     : VOPCX_Real_gfx10<0x0f8>;
defm V_CMPX_NGE_F16   : VOPCX_Real_gfx10<0x0f9>;
defm V_CMPX_NLG_F16   : VOPCX_Real_gfx10<0x0fa>;
defm V_CMPX_NGT_F16   : VOPCX_Real_gfx10<0x0fb>;
defm V_CMPX_NLE_F16   : VOPCX_Real_gfx10<0x0fc>;
defm V_CMPX_NEQ_F16   : VOPCX_Real_gfx10<0x0fd>;
defm V_CMPX_NLT_F16   : VOPCX_Real_gfx10<0x0fe>;
defm V_CMPX_TRU_F16   : VOPCX_Real_gfx10<0x0ff>;

//===----------------------------------------------------------------------===//
// GFX6, GFX7, GFX10.
//===----------------------------------------------------------------------===//

defm : VOPCInstAliases<NAME, "gfx6_gfx7">;
  }
} // End AssemblerPredicate = isGFX6GFX7

multiclass VOPC_Real_gfx6_gfx7_gfx10<bits<9> op> :
  VOPC_Real_gfx6_gfx7<op>, VOPC_Real_gfx10<op>;

multiclass VOPCX_Real_gfx6_gfx7<bits<9> op> :
  VOPC_Real_gfx6_gfx7<op>;

multiclass VOPCX_Real_gfx6_gfx7_gfx10 <bits<9> op> :
  VOPC_Real_gfx6_gfx7<op>, VOPCX_Real_gfx10<op>;

defm V_CMP_F_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x000>;
defm V_CMP_LT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x001>;
defm V_CMP_EQ_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x002>;
defm V_CMP_LE_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x003>;
defm V_CMP_GT_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x004>;
defm V_CMP_LG_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x005>;
defm V_CMP_GE_F32     : VOPC_Real_gfx6_gfx7_gfx10<0x006>;
defm V_CMP_O_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x007>;
defm V_CMP_U_F32      : VOPC_Real_gfx6_gfx7_gfx10<0x008>;
defm V_CMP_NGE_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x009>;
defm V_CMP_NLG_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00a>;
defm V_CMP_NGT_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00b>;
defm V_CMP_NLE_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00c>;
defm V_CMP_NEQ_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00d>;
defm V_CMP_NLT_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00e>;
defm V_CMP_TRU_F32    : VOPC_Real_gfx6_gfx7_gfx10<0x00f>;
defm V_CMPX_F_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x010>;
defm V_CMPX_LT_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x011>;
defm V_CMPX_EQ_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x012>;
defm V_CMPX_LE_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x013>;
defm V_CMPX_GT_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x014>;
defm V_CMPX_LG_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x015>;
defm V_CMPX_GE_F32    : VOPCX_Real_gfx6_gfx7_gfx10<0x016>;
defm V_CMPX_O_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x017>;
defm V_CMPX_U_F32     : VOPCX_Real_gfx6_gfx7_gfx10<0x018>;
defm V_CMPX_NGE_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x019>;
defm V_CMPX_NLG_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01a>;
defm V_CMPX_NGT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01b>;
defm V_CMPX_NLE_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01c>;
defm V_CMPX_NEQ_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01d>;
defm V_CMPX_NLT_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01e>;
defm V_CMPX_TRU_F32   : VOPCX_Real_gfx6_gfx7_gfx10<0x01f>;
defm V_CMP_F_F64      : VOPC_Real_gfx6_gfx7_gfx10<0x020>;
defm V_CMP_LT_F64     : VOPC_Real_gfx6_gfx7_gfx10<0x021>;
defm V_CMP_EQ_F64     : VOPC_Real_gfx6_gfx7_gfx10<0x022>;
defm V_CMP_LE_F64     : VOPC_Real_gfx6_gfx7_gfx10<0x023>;
defm V_CMP_GT_F64     : VOPC_Real_gfx6_gfx7_gfx10<0x024>;
defm V_CMP_LG_F64     : VOPC_Real_gfx6_gfx7_gfx10<0x025>;
defm V_CMP_GE_F64     : VOPC_Real_gfx6_gfx7_gfx10<0x026>;
defm V_CMP_O_F64      : VOPC_Real_gfx6_gfx7_gfx10<0x027>;
defm V_CMP_U_F64      : VOPC_Real_gfx6_gfx7_gfx10<0x028>;
defm V_CMP_NGE_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x029>;
defm V_CMP_NLG_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02a>;
defm V_CMP_NGT_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02b>;
defm V_CMP_NLE_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02c>;
defm V_CMP_NEQ_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02d>;
defm V_CMP_NLT_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02e>;
defm V_CMP_TRU_F64    : VOPC_Real_gfx6_gfx7_gfx10<0x02f>;
defm V_CMPX_F_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x030>;
defm V_CMPX_LT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x031>;
defm V_CMPX_EQ_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x032>;
defm V_CMPX_LE_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x033>;
defm V_CMPX_GT_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x034>;
defm V_CMPX_LG_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x035>;
defm V_CMPX_GE_F64    : VOPCX_Real_gfx6_gfx7_gfx10<0x036>;
defm V_CMPX_O_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x037>;
defm V_CMPX_U_F64     : VOPCX_Real_gfx6_gfx7_gfx10<0x038>;
defm V_CMPX_NGE_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x039>;
defm V_CMPX_NLG_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03a>;
defm V_CMPX_NGT_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03b>;
defm V_CMPX_NLE_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03c>;
defm V_CMPX_NEQ_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03d>;
defm V_CMPX_NLT_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03e>;
defm V_CMPX_TRU_F64   : VOPCX_Real_gfx6_gfx7_gfx10<0x03f>;
defm V_CMPS_F_F32     : VOPC_Real_gfx6_gfx7<0x040>;
defm V_CMPS_LT_F32    : VOPC_Real_gfx6_gfx7<0x041>;
defm V_CMPS_EQ_F32    : VOPC_Real_gfx6_gfx7<0x042>;
defm V_CMPS_LE_F32    : VOPC_Real_gfx6_gfx7<0x043>;
defm V_CMPS_GT_F32    : VOPC_Real_gfx6_gfx7<0x044>;
defm V_CMPS_LG_F32    : VOPC_Real_gfx6_gfx7<0x045>;
defm V_CMPS_GE_F32    : VOPC_Real_gfx6_gfx7<0x046>;
defm V_CMPS_O_F32     : VOPC_Real_gfx6_gfx7<0x047>;
defm V_CMPS_U_F32     : VOPC_Real_gfx6_gfx7<0x048>;
defm V_CMPS_NGE_F32   : VOPC_Real_gfx6_gfx7<0x049>;
defm V_CMPS_NLG_F32   : VOPC_Real_gfx6_gfx7<0x04a>;
defm V_CMPS_NGT_F32   : VOPC_Real_gfx6_gfx7<0x04b>;
defm V_CMPS_NLE_F32   : VOPC_Real_gfx6_gfx7<0x04c>;
defm V_CMPS_NEQ_F32   : VOPC_Real_gfx6_gfx7<0x04d>;
defm V_CMPS_NLT_F32   : VOPC_Real_gfx6_gfx7<0x04e>;
defm V_CMPS_TRU_F32   : VOPC_Real_gfx6_gfx7<0x04f>;
defm V_CMPSX_F_F32    : VOPCX_Real_gfx6_gfx7<0x050>;
defm V_CMPSX_LT_F32   : VOPCX_Real_gfx6_gfx7<0x051>;
defm V_CMPSX_EQ_F32   : VOPCX_Real_gfx6_gfx7<0x052>;
defm V_CMPSX_LE_F32   : VOPCX_Real_gfx6_gfx7<0x053>;
defm V_CMPSX_GT_F32   : VOPCX_Real_gfx6_gfx7<0x054>;
defm V_CMPSX_LG_F32   : VOPCX_Real_gfx6_gfx7<0x055>;
defm V_CMPSX_GE_F32   : VOPCX_Real_gfx6_gfx7<0x056>;
defm V_CMPSX_O_F32    : VOPCX_Real_gfx6_gfx7<0x057>;
defm V_CMPSX_U_F32    : VOPCX_Real_gfx6_gfx7<0x058>;
defm V_CMPSX_NGE_F32  : VOPCX_Real_gfx6_gfx7<0x059>;
defm V_CMPSX_NLG_F32  : VOPCX_Real_gfx6_gfx7<0x05a>;
defm V_CMPSX_NGT_F32  : VOPCX_Real_gfx6_gfx7<0x05b>;
defm V_CMPSX_NLE_F32  : VOPCX_Real_gfx6_gfx7<0x05c>;
defm V_CMPSX_NEQ_F32  : VOPCX_Real_gfx6_gfx7<0x05d>;
defm V_CMPSX_NLT_F32  : VOPCX_Real_gfx6_gfx7<0x05e>;
defm V_CMPSX_TRU_F32  : VOPCX_Real_gfx6_gfx7<0x05f>;
defm V_CMPS_F_F64     : VOPC_Real_gfx6_gfx7<0x060>;
defm V_CMPS_LT_F64    : VOPC_Real_gfx6_gfx7<0x061>;
defm V_CMPS_EQ_F64    : VOPC_Real_gfx6_gfx7<0x062>;
defm V_CMPS_LE_F64    : VOPC_Real_gfx6_gfx7<0x063>;
defm V_CMPS_GT_F64    : VOPC_Real_gfx6_gfx7<0x064>;
defm V_CMPS_LG_F64    : VOPC_Real_gfx6_gfx7<0x065>;
defm V_CMPS_GE_F64    : VOPC_Real_gfx6_gfx7<0x066>;
defm V_CMPS_O_F64     : VOPC_Real_gfx6_gfx7<0x067>;
defm V_CMPS_U_F64     : VOPC_Real_gfx6_gfx7<0x068>;
defm V_CMPS_NGE_F64   : VOPC_Real_gfx6_gfx7<0x069>;
defm V_CMPS_NLG_F64   : VOPC_Real_gfx6_gfx7<0x06a>;
defm V_CMPS_NGT_F64   : VOPC_Real_gfx6_gfx7<0x06b>;
defm V_CMPS_NLE_F64   : VOPC_Real_gfx6_gfx7<0x06c>;
defm V_CMPS_NEQ_F64   : VOPC_Real_gfx6_gfx7<0x06d>;
defm V_CMPS_NLT_F64   : VOPC_Real_gfx6_gfx7<0x06e>;
defm V_CMPS_TRU_F64   : VOPC_Real_gfx6_gfx7<0x06f>;
defm V_CMPSX_F_F64    : VOPCX_Real_gfx6_gfx7<0x070>;
defm V_CMPSX_LT_F64   : VOPCX_Real_gfx6_gfx7<0x071>;
defm V_CMPSX_EQ_F64   : VOPCX_Real_gfx6_gfx7<0x072>;
defm V_CMPSX_LE_F64   : VOPCX_Real_gfx6_gfx7<0x073>;
defm V_CMPSX_GT_F64   : VOPCX_Real_gfx6_gfx7<0x074>;
defm V_CMPSX_LG_F64   : VOPCX_Real_gfx6_gfx7<0x075>;
defm V_CMPSX_GE_F64   : VOPCX_Real_gfx6_gfx7<0x076>;
defm V_CMPSX_O_F64    : VOPCX_Real_gfx6_gfx7<0x077>;
defm V_CMPSX_U_F64    : VOPCX_Real_gfx6_gfx7<0x078>;
defm V_CMPSX_NGE_F64  : VOPCX_Real_gfx6_gfx7<0x079>;
defm V_CMPSX_NLG_F64  : VOPCX_Real_gfx6_gfx7<0x07a>;
defm V_CMPSX_NGT_F64  : VOPCX_Real_gfx6_gfx7<0x07b>;
defm V_CMPSX_NLE_F64  : VOPCX_Real_gfx6_gfx7<0x07c>;
defm V_CMPSX_NEQ_F64  : VOPCX_Real_gfx6_gfx7<0x07d>;
defm V_CMPSX_NLT_F64  : VOPCX_Real_gfx6_gfx7<0x07e>;
defm V_CMPSX_TRU_F64  : VOPCX_Real_gfx6_gfx7<0x07f>;
defm V_CMP_F_I32      : VOPC_Real_gfx6_gfx7_gfx10<0x080>;
defm V_CMP_LT_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x081>;
defm V_CMP_EQ_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x082>;
defm V_CMP_LE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x083>;
defm V_CMP_GT_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x084>;
defm V_CMP_NE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x085>;
defm V_CMP_GE_I32     : VOPC_Real_gfx6_gfx7_gfx10<0x086>;
defm V_CMP_T_I32      : VOPC_Real_gfx6_gfx7_gfx10<0x087>;
defm V_CMP_CLASS_F32  : VOPC_Real_gfx6_gfx7_gfx10<0x088>;
defm V_CMPX_F_I32     : VOPCX_Real_gfx6_gfx7_gfx10<0x090>;
defm V_CMPX_LT_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x091>;
defm V_CMPX_EQ_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x092>;
defm V_CMPX_LE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x093>;
defm V_CMPX_GT_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x094>;
defm V_CMPX_NE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x095>;
defm V_CMPX_GE_I32    : VOPCX_Real_gfx6_gfx7_gfx10<0x096>;
defm V_CMPX_T_I32     : VOPCX_Real_gfx6_gfx7_gfx10<0x097>;
defm V_CMPX_CLASS_F32 : VOPCX_Real_gfx6_gfx7_gfx10<0x098>;
defm V_CMP_F_I64      : VOPC_Real_gfx6_gfx7_gfx10<0x0a0>;
defm V_CMP_LT_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a1>;
defm V_CMP_EQ_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a2>;
defm V_CMP_LE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a3>;
defm V_CMP_GT_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a4>;
defm V_CMP_NE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a5>;
defm V_CMP_GE_I64     : VOPC_Real_gfx6_gfx7_gfx10<0x0a6>;
defm V_CMP_T_I64      : VOPC_Real_gfx6_gfx7_gfx10<0x0a7>;
defm V_CMP_CLASS_F64  : VOPC_Real_gfx6_gfx7_gfx10<0x0a8>;
defm V_CMPX_F_I64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0b0>;
defm V_CMPX_LT_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b1>;
defm V_CMPX_EQ_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b2>;
defm V_CMPX_LE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b3>;
defm V_CMPX_GT_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b4>;
defm V_CMPX_NE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b5>;
defm V_CMPX_GE_I64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0b6>;
defm V_CMPX_T_I64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0b7>;
defm V_CMPX_CLASS_F64 : VOPCX_Real_gfx6_gfx7_gfx10<0x0b8>;
defm V_CMP_F_U32      : VOPC_Real_gfx6_gfx7_gfx10<0x0c0>;
defm V_CMP_LT_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c1>;
defm V_CMP_EQ_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c2>;
defm V_CMP_LE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c3>;
defm V_CMP_GT_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c4>;
defm V_CMP_NE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c5>;
defm V_CMP_GE_U32     : VOPC_Real_gfx6_gfx7_gfx10<0x0c6>;
defm V_CMP_T_U32      : VOPC_Real_gfx6_gfx7_gfx10<0x0c7>;
defm V_CMPX_F_U32     : VOPCX_Real_gfx6_gfx7_gfx10<0x0d0>;
defm V_CMPX_LT_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d1>;
defm V_CMPX_EQ_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d2>;
defm V_CMPX_LE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d3>;
defm V_CMPX_GT_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d4>;
defm V_CMPX_NE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d5>;
defm V_CMPX_GE_U32    : VOPCX_Real_gfx6_gfx7_gfx10<0x0d6>;
defm V_CMPX_T_U32     : VOPCX_Real_gfx6_gfx7_gfx10<0x0d7>;
defm V_CMP_F_U64      : VOPC_Real_gfx6_gfx7_gfx10<0x0e0>;
defm V_CMP_LT_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e1>;
defm V_CMP_EQ_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e2>;
defm V_CMP_LE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e3>;
defm V_CMP_GT_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e4>;
defm V_CMP_NE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e5>;
defm V_CMP_GE_U64     : VOPC_Real_gfx6_gfx7_gfx10<0x0e6>;
defm V_CMP_T_U64      : VOPC_Real_gfx6_gfx7_gfx10<0x0e7>;
defm V_CMPX_F_U64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0f0>;
defm V_CMPX_LT_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f1>;
defm V_CMPX_EQ_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f2>;
defm V_CMPX_LE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f3>;
defm V_CMPX_GT_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f4>;
defm V_CMPX_NE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f5>;
defm V_CMPX_GE_U64    : VOPCX_Real_gfx6_gfx7_gfx10<0x0f6>;
defm V_CMPX_T_U64     : VOPCX_Real_gfx6_gfx7_gfx10<0x0f7>;

//===----------------------------------------------------------------------===//
// GFX8, GFX9 (VI).
//===----------------------------------------------------------------------===//

multiclass VOPC_Real_vi <bits<10> op> {
  let AssemblerPredicate = isGFX8GFX9, DecoderNamespace = "GFX8" in {
    def _e32_vi :
      VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
      VOPCe<op{7-0}>;

def _e64_vi :
      VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
      VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
      // Encoding used for VOPC instructions encoded as VOP3
      // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
      bits<8> sdst;
      let Inst{7-0} = sdst;
    }
  }

foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA>.ret in
  def _sdwa_vi :
    VOP_SDWA_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
    VOPC_SDWAe <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;

foreach _ = BoolToList<!cast<VOPC_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9>.ret in
  def _sdwa_gfx9 :
    VOP_SDWA9_Real <!cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa")>,
    VOPC_SDWA9e <op{7-0}, !cast<VOPC_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;

let AssemblerPredicate = isGFX8GFX9 in {
    defm : VOPCInstAliases<NAME, "vi">;
  }
}

defm V_CMP_CLASS_F32  : VOPC_Real_vi <0x10>;
defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>;
defm V_CMP_CLASS_F64  : VOPC_Real_vi <0x12>;
defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>;
defm V_CMP_CLASS_F16  : VOPC_Real_vi <0x14>;
defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>;

defm V_CMP_F_F16      : VOPC_Real_vi <0x20>;
defm V_CMP_LT_F16     : VOPC_Real_vi <0x21>;
defm V_CMP_EQ_F16     : VOPC_Real_vi <0x22>;
defm V_CMP_LE_F16     : VOPC_Real_vi <0x23>;
defm V_CMP_GT_F16     : VOPC_Real_vi <0x24>;
defm V_CMP_LG_F16     : VOPC_Real_vi <0x25>;
defm V_CMP_GE_F16     : VOPC_Real_vi <0x26>;
defm V_CMP_O_F16      : VOPC_Real_vi <0x27>;
defm V_CMP_U_F16      : VOPC_Real_vi <0x28>;
defm V_CMP_NGE_F16    : VOPC_Real_vi <0x29>;
defm V_CMP_NLG_F16    : VOPC_Real_vi <0x2a>;
defm V_CMP_NGT_F16    : VOPC_Real_vi <0x2b>;
defm V_CMP_NLE_F16    : VOPC_Real_vi <0x2c>;
defm V_CMP_NEQ_F16    : VOPC_Real_vi <0x2d>;
defm V_CMP_NLT_F16    : VOPC_Real_vi <0x2e>;
defm V_CMP_TRU_F16    : VOPC_Real_vi <0x2f>;

defm V_CMPX_F_F16     : VOPC_Real_vi <0x30>;
defm V_CMPX_LT_F16    : VOPC_Real_vi <0x31>;
defm V_CMPX_EQ_F16    : VOPC_Real_vi <0x32>;
defm V_CMPX_LE_F16    : VOPC_Real_vi <0x33>;
defm V_CMPX_GT_F16    : VOPC_Real_vi <0x34>;
defm V_CMPX_LG_F16    : VOPC_Real_vi <0x35>;
defm V_CMPX_GE_F16    : VOPC_Real_vi <0x36>;
defm V_CMPX_O_F16     : VOPC_Real_vi <0x37>;
defm V_CMPX_U_F16     : VOPC_Real_vi <0x38>;
defm V_CMPX_NGE_F16   : VOPC_Real_vi <0x39>;
defm V_CMPX_NLG_F16   : VOPC_Real_vi <0x3a>;
defm V_CMPX_NGT_F16   : VOPC_Real_vi <0x3b>;
defm V_CMPX_NLE_F16   : VOPC_Real_vi <0x3c>;
defm V_CMPX_NEQ_F16   : VOPC_Real_vi <0x3d>;
defm V_CMPX_NLT_F16   : VOPC_Real_vi <0x3e>;
defm V_CMPX_TRU_F16   : VOPC_Real_vi <0x3f>;

defm V_CMP_F_F32      : VOPC_Real_vi <0x40>;
defm V_CMP_LT_F32     : VOPC_Real_vi <0x41>;
defm V_CMP_EQ_F32     : VOPC_Real_vi <0x42>;
defm V_CMP_LE_F32     : VOPC_Real_vi <0x43>;
defm V_CMP_GT_F32     : VOPC_Real_vi <0x44>;
defm V_CMP_LG_F32     : VOPC_Real_vi <0x45>;
defm V_CMP_GE_F32     : VOPC_Real_vi <0x46>;
defm V_CMP_O_F32      : VOPC_Real_vi <0x47>;
defm V_CMP_U_F32      : VOPC_Real_vi <0x48>;
defm V_CMP_NGE_F32    : VOPC_Real_vi <0x49>;
defm V_CMP_NLG_F32    : VOPC_Real_vi <0x4a>;
defm V_CMP_NGT_F32    : VOPC_Real_vi <0x4b>;
defm V_CMP_NLE_F32    : VOPC_Real_vi <0x4c>;
defm V_CMP_NEQ_F32    : VOPC_Real_vi <0x4d>;
defm V_CMP_NLT_F32    : VOPC_Real_vi <0x4e>;
defm V_CMP_TRU_F32    : VOPC_Real_vi <0x4f>;

defm V_CMPX_F_F32     : VOPC_Real_vi <0x50>;
defm V_CMPX_LT_F32    : VOPC_Real_vi <0x51>;
defm V_CMPX_EQ_F32    : VOPC_Real_vi <0x52>;
defm V_CMPX_LE_F32    : VOPC_Real_vi <0x53>;
defm V_CMPX_GT_F32    : VOPC_Real_vi <0x54>;
defm V_CMPX_LG_F32    : VOPC_Real_vi <0x55>;
defm V_CMPX_GE_F32    : VOPC_Real_vi <0x56>;
defm V_CMPX_O_F32     : VOPC_Real_vi <0x57>;
defm V_CMPX_U_F32     : VOPC_Real_vi <0x58>;
defm V_CMPX_NGE_F32   : VOPC_Real_vi <0x59>;
defm V_CMPX_NLG_F32   : VOPC_Real_vi <0x5a>;
defm V_CMPX_NGT_F32   : VOPC_Real_vi <0x5b>;
defm V_CMPX_NLE_F32   : VOPC_Real_vi <0x5c>;
defm V_CMPX_NEQ_F32   : VOPC_Real_vi <0x5d>;
defm V_CMPX_NLT_F32   : VOPC_Real_vi <0x5e>;
defm V_CMPX_TRU_F32   : VOPC_Real_vi <0x5f>;

defm V_CMP_F_F64      : VOPC_Real_vi <0x60>;
defm V_CMP_LT_F64     : VOPC_Real_vi <0x61>;
defm V_CMP_EQ_F64     : VOPC_Real_vi <0x62>;
defm V_CMP_LE_F64     : VOPC_Real_vi <0x63>;
defm V_CMP_GT_F64     : VOPC_Real_vi <0x64>;
defm V_CMP_LG_F64     : VOPC_Real_vi <0x65>;
defm V_CMP_GE_F64     : VOPC_Real_vi <0x66>;
defm V_CMP_O_F64      : VOPC_Real_vi <0x67>;
defm V_CMP_U_F64      : VOPC_Real_vi <0x68>;
defm V_CMP_NGE_F64    : VOPC_Real_vi <0x69>;
defm V_CMP_NLG_F64    : VOPC_Real_vi <0x6a>;
defm V_CMP_NGT_F64    : VOPC_Real_vi <0x6b>;
defm V_CMP_NLE_F64    : VOPC_Real_vi <0x6c>;
defm V_CMP_NEQ_F64    : VOPC_Real_vi <0x6d>;
defm V_CMP_NLT_F64    : VOPC_Real_vi <0x6e>;
defm V_CMP_TRU_F64    : VOPC_Real_vi <0x6f>;

defm V_CMPX_F_F64     : VOPC_Real_vi <0x70>;
defm V_CMPX_LT_F64    : VOPC_Real_vi <0x71>;
defm V_CMPX_EQ_F64    : VOPC_Real_vi <0x72>;
defm V_CMPX_LE_F64    : VOPC_Real_vi <0x73>;
defm V_CMPX_GT_F64    : VOPC_Real_vi <0x74>;
defm V_CMPX_LG_F64    : VOPC_Real_vi <0x75>;
defm V_CMPX_GE_F64    : VOPC_Real_vi <0x76>;
defm V_CMPX_O_F64     : VOPC_Real_vi <0x77>;
defm V_CMPX_U_F64     : VOPC_Real_vi <0x78>;
defm V_CMPX_NGE_F64   : VOPC_Real_vi <0x79>;
defm V_CMPX_NLG_F64   : VOPC_Real_vi <0x7a>;
defm V_CMPX_NGT_F64   : VOPC_Real_vi <0x7b>;
defm V_CMPX_NLE_F64   : VOPC_Real_vi <0x7c>;
defm V_CMPX_NEQ_F64   : VOPC_Real_vi <0x7d>;
defm V_CMPX_NLT_F64   : VOPC_Real_vi <0x7e>;
defm V_CMPX_TRU_F64   : VOPC_Real_vi <0x7f>;

defm V_CMP_F_I16      : VOPC_Real_vi <0xa0>;
defm V_CMP_LT_I16     : VOPC_Real_vi <0xa1>;
defm V_CMP_EQ_I16     : VOPC_Real_vi <0xa2>;
defm V_CMP_LE_I16     : VOPC_Real_vi <0xa3>;
defm V_CMP_GT_I16     : VOPC_Real_vi <0xa4>;
defm V_CMP_NE_I16     : VOPC_Real_vi <0xa5>;
defm V_CMP_GE_I16     : VOPC_Real_vi <0xa6>;
defm V_CMP_T_I16      : VOPC_Real_vi <0xa7>;

defm V_CMP_F_U16      : VOPC_Real_vi <0xa8>;
defm V_CMP_LT_U16     : VOPC_Real_vi <0xa9>;
defm V_CMP_EQ_U16     : VOPC_Real_vi <0xaa>;
defm V_CMP_LE_U16     : VOPC_Real_vi <0xab>;
defm V_CMP_GT_U16     : VOPC_Real_vi <0xac>;
defm V_CMP_NE_U16     : VOPC_Real_vi <0xad>;
defm V_CMP_GE_U16     : VOPC_Real_vi <0xae>;
defm V_CMP_T_U16      : VOPC_Real_vi <0xaf>;

defm V_CMPX_F_I16 : VOPC_Real_vi <0xb0>;
defm V_CMPX_LT_I16 : VOPC_Real_vi <0xb1>;
defm V_CMPX_EQ_I16 : VOPC_Real_vi <0xb2>;
defm V_CMPX_LE_I16 : VOPC_Real_vi <0xb3>;
defm V_CMPX_GT_I16 : VOPC_Real_vi <0xb4>;
defm V_CMPX_NE_I16 : VOPC_Real_vi <0xb5>;
defm V_CMPX_GE_I16 : VOPC_Real_vi <0xb6>;
defm V_CMPX_T_I16 : VOPC_Real_vi <0xb7>;

defm V_CMPX_F_U16 : VOPC_Real_vi <0xb8>;
defm V_CMPX_LT_U16 : VOPC_Real_vi <0xb9>;
defm V_CMPX_EQ_U16 : VOPC_Real_vi <0xba>;
defm V_CMPX_LE_U16 : VOPC_Real_vi <0xbb>;
defm V_CMPX_GT_U16 : VOPC_Real_vi <0xbc>;
defm V_CMPX_NE_U16 : VOPC_Real_vi <0xbd>;
defm V_CMPX_GE_U16 : VOPC_Real_vi <0xbe>;
defm V_CMPX_T_U16 : VOPC_Real_vi <0xbf>;

defm V_CMP_F_I32      : VOPC_Real_vi <0xc0>;
defm V_CMP_LT_I32     : VOPC_Real_vi <0xc1>;
defm V_CMP_EQ_I32     : VOPC_Real_vi <0xc2>;
defm V_CMP_LE_I32     : VOPC_Real_vi <0xc3>;
defm V_CMP_GT_I32     : VOPC_Real_vi <0xc4>;
defm V_CMP_NE_I32     : VOPC_Real_vi <0xc5>;
defm V_CMP_GE_I32     : VOPC_Real_vi <0xc6>;
defm V_CMP_T_I32      : VOPC_Real_vi <0xc7>;

defm V_CMPX_F_I32     : VOPC_Real_vi <0xd0>;
defm V_CMPX_LT_I32    : VOPC_Real_vi <0xd1>;
defm V_CMPX_EQ_I32    : VOPC_Real_vi <0xd2>;
defm V_CMPX_LE_I32    : VOPC_Real_vi <0xd3>;
defm V_CMPX_GT_I32    : VOPC_Real_vi <0xd4>;
defm V_CMPX_NE_I32    : VOPC_Real_vi <0xd5>;
defm V_CMPX_GE_I32    : VOPC_Real_vi <0xd6>;
defm V_CMPX_T_I32     : VOPC_Real_vi <0xd7>;

defm V_CMP_F_I64      : VOPC_Real_vi <0xe0>;
defm V_CMP_LT_I64     : VOPC_Real_vi <0xe1>;
defm V_CMP_EQ_I64     : VOPC_Real_vi <0xe2>;
defm V_CMP_LE_I64     : VOPC_Real_vi <0xe3>;
defm V_CMP_GT_I64     : VOPC_Real_vi <0xe4>;
defm V_CMP_NE_I64     : VOPC_Real_vi <0xe5>;
defm V_CMP_GE_I64     : VOPC_Real_vi <0xe6>;
defm V_CMP_T_I64      : VOPC_Real_vi <0xe7>;

defm V_CMPX_F_I64     : VOPC_Real_vi <0xf0>;
defm V_CMPX_LT_I64    : VOPC_Real_vi <0xf1>;
defm V_CMPX_EQ_I64    : VOPC_Real_vi <0xf2>;
defm V_CMPX_LE_I64    : VOPC_Real_vi <0xf3>;
defm V_CMPX_GT_I64    : VOPC_Real_vi <0xf4>;
defm V_CMPX_NE_I64    : VOPC_Real_vi <0xf5>;
defm V_CMPX_GE_I64    : VOPC_Real_vi <0xf6>;
defm V_CMPX_T_I64     : VOPC_Real_vi <0xf7>;

defm V_CMP_F_U32      : VOPC_Real_vi <0xc8>;
defm V_CMP_LT_U32     : VOPC_Real_vi <0xc9>;
defm V_CMP_EQ_U32     : VOPC_Real_vi <0xca>;
defm V_CMP_LE_U32     : VOPC_Real_vi <0xcb>;
defm V_CMP_GT_U32     : VOPC_Real_vi <0xcc>;
defm V_CMP_NE_U32     : VOPC_Real_vi <0xcd>;
defm V_CMP_GE_U32     : VOPC_Real_vi <0xce>;
defm V_CMP_T_U32      : VOPC_Real_vi <0xcf>;

defm V_CMPX_F_U32     : VOPC_Real_vi <0xd8>;
defm V_CMPX_LT_U32    : VOPC_Real_vi <0xd9>;
defm V_CMPX_EQ_U32    : VOPC_Real_vi <0xda>;
defm V_CMPX_LE_U32    : VOPC_Real_vi <0xdb>;
defm V_CMPX_GT_U32    : VOPC_Real_vi <0xdc>;
defm V_CMPX_NE_U32    : VOPC_Real_vi <0xdd>;
defm V_CMPX_GE_U32    : VOPC_Real_vi <0xde>;
defm V_CMPX_T_U32     : VOPC_Real_vi <0xdf>;

defm V_CMP_F_U64      : VOPC_Real_vi <0xe8>;
defm V_CMP_LT_U64     : VOPC_Real_vi <0xe9>;
defm V_CMP_EQ_U64     : VOPC_Real_vi <0xea>;
defm V_CMP_LE_U64     : VOPC_Real_vi <0xeb>;
defm V_CMP_GT_U64     : VOPC_Real_vi <0xec>;
defm V_CMP_NE_U64     : VOPC_Real_vi <0xed>;
defm V_CMP_GE_U64     : VOPC_Real_vi <0xee>;
defm V_CMP_T_U64      : VOPC_Real_vi <0xef>;

defm V_CMPX_F_U64     : VOPC_Real_vi <0xf8>;
defm V_CMPX_LT_U64    : VOPC_Real_vi <0xf9>;
defm V_CMPX_EQ_U64    : VOPC_Real_vi <0xfa>;
defm V_CMPX_LE_U64    : VOPC_Real_vi <0xfb>;
defm V_CMPX_GT_U64    : VOPC_Real_vi <0xfc>;
defm V_CMPX_NE_U64    : VOPC_Real_vi <0xfd>;
defm V_CMPX_GE_U64    : VOPC_Real_vi <0xfe>;
defm V_CMPX_T_U64     : VOPC_Real_vi <0xff>;

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