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usr / src / contrib / llvm-project / llvm / lib / Target / WebAssembly /

📁 ..
📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 README.txt(8.34 KB)
📁 TargetInfo
📄 WebAssembly.h(4.05 KB)
📄 WebAssembly.td(4.85 KB)
📄 WebAssemblyAddMissingPrototypes.cpp(5.41 KB)
📄 WebAssemblyArgumentMove.cpp(3.36 KB)
📄 WebAssemblyAsmPrinter.cpp(16.09 KB)
📄 WebAssemblyAsmPrinter.h(3.12 KB)
📄 WebAssemblyCFGSort.cpp(15.94 KB)
📄 WebAssemblyCFGStackify.cpp(55.56 KB)
📄 WebAssemblyDebugFixup.cpp(5.4 KB)
📄 WebAssemblyDebugValueManager.cpp(1.77 KB)
📄 WebAssemblyDebugValueManager.h(1.13 KB)
📄 WebAssemblyExceptionInfo.cpp(6.23 KB)
📄 WebAssemblyExceptionInfo.h(6.24 KB)
📄 WebAssemblyExplicitLocals.cpp(15.04 KB)
📄 WebAssemblyFastISel.cpp(40.39 KB)
📄 WebAssemblyFixBrTableDefaults.cpp(5.81 KB)
📄 WebAssemblyFixFunctionBitcasts.cpp(12.59 KB)
📄 WebAssemblyFixIrreducibleControlFlow.cpp(18.91 KB)
📄 WebAssemblyFrameLowering.cpp(12.68 KB)
📄 WebAssemblyFrameLowering.h(2.98 KB)
📄 WebAssemblyISD.def(1.17 KB)
📄 WebAssemblyISelDAGToDAG.cpp(9.08 KB)
📄 WebAssemblyISelLowering.cpp(68.59 KB)
📄 WebAssemblyISelLowering.h(5.85 KB)
📄 WebAssemblyInstrAtomics.td(48.5 KB)
📄 WebAssemblyInstrBulkMemory.td(2.84 KB)
📄 WebAssemblyInstrCall.td(3.21 KB)
📄 WebAssemblyInstrControl.td(7.93 KB)
📄 WebAssemblyInstrConv.td(14.1 KB)
📄 WebAssemblyInstrFloat.td(6.03 KB)
📄 WebAssemblyInstrFormats.td(3.1 KB)
📄 WebAssemblyInstrInfo.cpp(8.21 KB)
📄 WebAssemblyInstrInfo.h(2.63 KB)
📄 WebAssemblyInstrInfo.td(14.37 KB)
📄 WebAssemblyInstrInteger.td(6.05 KB)
📄 WebAssemblyInstrMemory.td(18.63 KB)
📄 WebAssemblyInstrRef.td(1.15 KB)
📄 WebAssemblyInstrSIMD.td(39.08 KB)
📄 WebAssemblyLateEHPrepare.cpp(14.57 KB)
📄 WebAssemblyLowerBrUnless.cpp(6.21 KB)
📄 WebAssemblyLowerEmscriptenEHSjLj.cpp(45.45 KB)
📄 WebAssemblyLowerGlobalDtors.cpp(7.79 KB)
📄 WebAssemblyMCInstLower.cpp(13.72 KB)
📄 WebAssemblyMCInstLower.h(1.63 KB)
📄 WebAssemblyMachineFunctionInfo.cpp(4.29 KB)
📄 WebAssemblyMachineFunctionInfo.h(6.75 KB)
📄 WebAssemblyMemIntrinsicResults.cpp(7.39 KB)
📄 WebAssemblyOptimizeLiveIntervals.cpp(4.61 KB)
📄 WebAssemblyOptimizeReturned.cpp(2.46 KB)
📄 WebAssemblyPeephole.cpp(6.33 KB)
📄 WebAssemblyPrepareForLiveIntervals.cpp(4.34 KB)
📄 WebAssemblyRegColoring.cpp(6.37 KB)
📄 WebAssemblyRegNumbering.cpp(3.86 KB)
📄 WebAssemblyRegStackify.cpp(38.22 KB)
📄 WebAssemblyRegisterInfo.cpp(6.21 KB)
📄 WebAssemblyRegisterInfo.h(1.74 KB)
📄 WebAssemblyRegisterInfo.td(2.83 KB)
📄 WebAssemblyReplacePhysRegs.cpp(3.89 KB)
📄 WebAssemblyRuntimeLibcallSignatures.cpp(33.82 KB)
📄 WebAssemblyRuntimeLibcallSignatures.h(1.37 KB)
📄 WebAssemblySelectionDAGInfo.cpp(2.57 KB)
📄 WebAssemblySelectionDAGInfo.h(1.94 KB)
📄 WebAssemblySetP2AlignOperands.cpp(3.32 KB)
📄 WebAssemblySubtarget.cpp(2.18 KB)
📄 WebAssemblySubtarget.h(3.88 KB)
📄 WebAssemblyTargetMachine.cpp(18.85 KB)
📄 WebAssemblyTargetMachine.h(2.29 KB)
📄 WebAssemblyTargetObjectFile.cpp(886 B)
📄 WebAssemblyTargetObjectFile.h(959 B)
📄 WebAssemblyTargetTransformInfo.cpp(2.9 KB)
📄 WebAssemblyTargetTransformInfo.h(2.5 KB)
📄 WebAssemblyUtilities.cpp(3.43 KB)
📄 WebAssemblyUtilities.h(1.8 KB)
📄 known_gcc_test_failures.txt(2.07 KB)

Editing: WebAssemblyInstrInfo.cpp

//===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file contains the WebAssembly implementation of the
/// TargetInstrInfo class.
///
//===----------------------------------------------------------------------===//

#include "WebAssemblyInstrInfo.h"
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "WebAssembly.h"
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
using namespace llvm;

#define DEBUG_TYPE "wasm-instr-info"

#define GET_INSTRINFO_CTOR_DTOR
#include "WebAssemblyGenInstrInfo.inc"

// defines WebAssembly::getNamedOperandIdx
#define GET_INSTRINFO_NAMED_OPS
#include "WebAssemblyGenInstrInfo.inc"

WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
    : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
                              WebAssembly::ADJCALLSTACKUP,
                              WebAssembly::CATCHRET),
      RI(STI.getTargetTriple()) {}

bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
    const MachineInstr &MI, AAResults *AA) const {
  switch (MI.getOpcode()) {
  case WebAssembly::CONST_I32:
  case WebAssembly::CONST_I64:
  case WebAssembly::CONST_F32:
  case WebAssembly::CONST_F64:
    // isReallyTriviallyReMaterializableGeneric misses these because of the
    // ARGUMENTS implicit def, so we manualy override it here.
    return true;
  default:
    return false;
  }
}

void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                       MachineBasicBlock::iterator I,
                                       const DebugLoc &DL, MCRegister DestReg,
                                       MCRegister SrcReg, bool KillSrc) const {
  // This method is called by post-RA expansion, which expects only pregs to
  // exist. However we need to handle both here.
  auto &MRI = MBB.getParent()->getRegInfo();
  const TargetRegisterClass *RC =
      Register::isVirtualRegister(DestReg)
          ? MRI.getRegClass(DestReg)
          : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);

unsigned CopyOpcode;
  if (RC == &WebAssembly::I32RegClass)
    CopyOpcode = WebAssembly::COPY_I32;
  else if (RC == &WebAssembly::I64RegClass)
    CopyOpcode = WebAssembly::COPY_I64;
  else if (RC == &WebAssembly::F32RegClass)
    CopyOpcode = WebAssembly::COPY_F32;
  else if (RC == &WebAssembly::F64RegClass)
    CopyOpcode = WebAssembly::COPY_F64;
  else if (RC == &WebAssembly::V128RegClass)
    CopyOpcode = WebAssembly::COPY_V128;
  else if (RC == &WebAssembly::EXNREFRegClass)
    CopyOpcode = WebAssembly::COPY_EXNREF;
  else
    llvm_unreachable("Unexpected register class");

BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
      .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
}

MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(
    MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
  // If the operands are stackified, we can't reorder them.
  WebAssemblyFunctionInfo &MFI =
      *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
  if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
      MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
    return nullptr;

// Otherwise use the default implementation.
  return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
}

// Branch analysis.
bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                         MachineBasicBlock *&TBB,
                                         MachineBasicBlock *&FBB,
                                         SmallVectorImpl<MachineOperand> &Cond,
                                         bool /*AllowModify*/) const {
  const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
  // WebAssembly has control flow that doesn't have explicit branches or direct
  // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
  // is created after CFGStackify.
  if (MFI.isCFGStackified())
    return true;

bool HaveCond = false;
  for (MachineInstr &MI : MBB.terminators()) {
    switch (MI.getOpcode()) {
    default:
      // Unhandled instruction; bail out.
      return true;
    case WebAssembly::BR_IF:
      if (HaveCond)
        return true;
      Cond.push_back(MachineOperand::CreateImm(true));
      Cond.push_back(MI.getOperand(1));
      TBB = MI.getOperand(0).getMBB();
      HaveCond = true;
      break;
    case WebAssembly::BR_UNLESS:
      if (HaveCond)
        return true;
      Cond.push_back(MachineOperand::CreateImm(false));
      Cond.push_back(MI.getOperand(1));
      TBB = MI.getOperand(0).getMBB();
      HaveCond = true;
      break;
    case WebAssembly::BR:
      if (!HaveCond)
        TBB = MI.getOperand(0).getMBB();
      else
        FBB = MI.getOperand(0).getMBB();
      break;
    case WebAssembly::BR_ON_EXN:
      if (HaveCond)
        return true;
      Cond.push_back(MachineOperand::CreateImm(true));
      Cond.push_back(MI.getOperand(2));
      TBB = MI.getOperand(0).getMBB();
      HaveCond = true;
      break;
    }
    if (MI.isBarrier())
      break;
  }

return false;
}

unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                            int *BytesRemoved) const {
  assert(!BytesRemoved && "code size not handled");

MachineBasicBlock::instr_iterator I = MBB.instr_end();
  unsigned Count = 0;

while (I != MBB.instr_begin()) {
    --I;
    if (I->isDebugInstr())
      continue;
    if (!I->isTerminator())
      break;
    // Remove the branch.
    I->eraseFromParent();
    I = MBB.instr_end();
    ++Count;
  }

return Count;
}

unsigned WebAssemblyInstrInfo::insertBranch(
    MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
    ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
  assert(!BytesAdded && "code size not handled");

if (Cond.empty()) {
    if (!TBB)
      return 0;

BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
    return 1;
  }

assert(Cond.size() == 2 && "Expected a flag and a successor block");

MachineFunction &MF = *MBB.getParent();
  auto &MRI = MF.getRegInfo();
  bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
                                          &WebAssembly::EXNREFRegClass;

if (Cond[0].getImm()) {
    if (IsBrOnExn) {
      const char *CPPExnSymbol = MF.createExternalSymbolName("__cpp_exception");
      BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
          .addMBB(TBB)
          .addExternalSymbol(CPPExnSymbol)
          .add(Cond[1]);
    } else
      BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
  } else {
    assert(!IsBrOnExn && "br_on_exn does not have a reversed condition");
    BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
  }
  if (!FBB)
    return 1;

BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
  return 2;
}

bool WebAssemblyInstrInfo::reverseBranchCondition(
    SmallVectorImpl<MachineOperand> &Cond) const {
  assert(Cond.size() == 2 && "Expected a flag and a condition expression");

// br_on_exn's condition cannot be reversed
  MachineFunction &MF = *Cond[1].getParent()->getParent()->getParent();
  auto &MRI = MF.getRegInfo();
  if (Cond[1].isReg() &&
      MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
    return true;

Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
  return false;
}

ArrayRef<std::pair<int, const char *>>
WebAssemblyInstrInfo::getSerializableTargetIndices() const {
  static const std::pair<int, const char *> TargetIndices[] = {
      {WebAssembly::TI_LOCAL, "wasm-local"},
      {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
      {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
      {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"}};
  return makeArrayRef(TargetIndices);
}

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Editing: WebAssemblyInstrInfo.cpp

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