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usr / src / contrib / llvm-project / llvm / lib / Target / WebAssembly /

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📁 AsmParser
📁 Disassembler
📁 MCTargetDesc
📄 README.txt(8.34 KB)
📁 TargetInfo
📄 WebAssembly.h(4.05 KB)
📄 WebAssembly.td(4.85 KB)
📄 WebAssemblyAddMissingPrototypes.cpp(5.41 KB)
📄 WebAssemblyArgumentMove.cpp(3.36 KB)
📄 WebAssemblyAsmPrinter.cpp(16.09 KB)
📄 WebAssemblyAsmPrinter.h(3.12 KB)
📄 WebAssemblyCFGSort.cpp(15.94 KB)
📄 WebAssemblyCFGStackify.cpp(55.56 KB)
📄 WebAssemblyDebugFixup.cpp(5.4 KB)
📄 WebAssemblyDebugValueManager.cpp(1.77 KB)
📄 WebAssemblyDebugValueManager.h(1.13 KB)
📄 WebAssemblyExceptionInfo.cpp(6.23 KB)
📄 WebAssemblyExceptionInfo.h(6.24 KB)
📄 WebAssemblyExplicitLocals.cpp(15.04 KB)
📄 WebAssemblyFastISel.cpp(40.39 KB)
📄 WebAssemblyFixBrTableDefaults.cpp(5.81 KB)
📄 WebAssemblyFixFunctionBitcasts.cpp(12.59 KB)
📄 WebAssemblyFixIrreducibleControlFlow.cpp(18.91 KB)
📄 WebAssemblyFrameLowering.cpp(12.68 KB)
📄 WebAssemblyFrameLowering.h(2.98 KB)
📄 WebAssemblyISD.def(1.17 KB)
📄 WebAssemblyISelDAGToDAG.cpp(9.08 KB)
📄 WebAssemblyISelLowering.cpp(68.59 KB)
📄 WebAssemblyISelLowering.h(5.85 KB)
📄 WebAssemblyInstrAtomics.td(48.5 KB)
📄 WebAssemblyInstrBulkMemory.td(2.84 KB)
📄 WebAssemblyInstrCall.td(3.21 KB)
📄 WebAssemblyInstrControl.td(7.93 KB)
📄 WebAssemblyInstrConv.td(14.1 KB)
📄 WebAssemblyInstrFloat.td(6.03 KB)
📄 WebAssemblyInstrFormats.td(3.1 KB)
📄 WebAssemblyInstrInfo.cpp(8.21 KB)
📄 WebAssemblyInstrInfo.h(2.63 KB)
📄 WebAssemblyInstrInfo.td(14.37 KB)
📄 WebAssemblyInstrInteger.td(6.05 KB)
📄 WebAssemblyInstrMemory.td(18.63 KB)
📄 WebAssemblyInstrRef.td(1.15 KB)
📄 WebAssemblyInstrSIMD.td(39.08 KB)
📄 WebAssemblyLateEHPrepare.cpp(14.57 KB)
📄 WebAssemblyLowerBrUnless.cpp(6.21 KB)
📄 WebAssemblyLowerEmscriptenEHSjLj.cpp(45.45 KB)
📄 WebAssemblyLowerGlobalDtors.cpp(7.79 KB)
📄 WebAssemblyMCInstLower.cpp(13.72 KB)
📄 WebAssemblyMCInstLower.h(1.63 KB)
📄 WebAssemblyMachineFunctionInfo.cpp(4.29 KB)
📄 WebAssemblyMachineFunctionInfo.h(6.75 KB)
📄 WebAssemblyMemIntrinsicResults.cpp(7.39 KB)
📄 WebAssemblyOptimizeLiveIntervals.cpp(4.61 KB)
📄 WebAssemblyOptimizeReturned.cpp(2.46 KB)
📄 WebAssemblyPeephole.cpp(6.33 KB)
📄 WebAssemblyPrepareForLiveIntervals.cpp(4.34 KB)
📄 WebAssemblyRegColoring.cpp(6.37 KB)
📄 WebAssemblyRegNumbering.cpp(3.86 KB)
📄 WebAssemblyRegStackify.cpp(38.22 KB)
📄 WebAssemblyRegisterInfo.cpp(6.21 KB)
📄 WebAssemblyRegisterInfo.h(1.74 KB)
📄 WebAssemblyRegisterInfo.td(2.83 KB)
📄 WebAssemblyReplacePhysRegs.cpp(3.89 KB)
📄 WebAssemblyRuntimeLibcallSignatures.cpp(33.82 KB)
📄 WebAssemblyRuntimeLibcallSignatures.h(1.37 KB)
📄 WebAssemblySelectionDAGInfo.cpp(2.57 KB)
📄 WebAssemblySelectionDAGInfo.h(1.94 KB)
📄 WebAssemblySetP2AlignOperands.cpp(3.32 KB)
📄 WebAssemblySubtarget.cpp(2.18 KB)
📄 WebAssemblySubtarget.h(3.88 KB)
📄 WebAssemblyTargetMachine.cpp(18.85 KB)
📄 WebAssemblyTargetMachine.h(2.29 KB)
📄 WebAssemblyTargetObjectFile.cpp(886 B)
📄 WebAssemblyTargetObjectFile.h(959 B)
📄 WebAssemblyTargetTransformInfo.cpp(2.9 KB)
📄 WebAssemblyTargetTransformInfo.h(2.5 KB)
📄 WebAssemblyUtilities.cpp(3.43 KB)
📄 WebAssemblyUtilities.h(1.8 KB)
📄 known_gcc_test_failures.txt(2.07 KB)

Editing: WebAssemblyLowerBrUnless.cpp

//===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file lowers br_unless into br_if with an inverted condition.
///
/// br_unless is not currently in the spec, but it's very convenient for LLVM
/// to use. This pass allows LLVM to use it, for now.
///
//===----------------------------------------------------------------------===//

#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "WebAssembly.h"
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;

#define DEBUG_TYPE "wasm-lower-br_unless"

namespace {
class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
  StringRef getPassName() const override {
    return "WebAssembly Lower br_unless";
  }

void getAnalysisUsage(AnalysisUsage &AU) const override {
    AU.setPreservesCFG();
    MachineFunctionPass::getAnalysisUsage(AU);
  }

bool runOnMachineFunction(MachineFunction &MF) override;

public:
  static char ID; // Pass identification, replacement for typeid
  WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
};
} // end anonymous namespace

char WebAssemblyLowerBrUnless::ID = 0;
INITIALIZE_PASS(WebAssemblyLowerBrUnless, DEBUG_TYPE,
                "Lowers br_unless into inverted br_if", false, false)

FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
  return new WebAssemblyLowerBrUnless();
}

bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
  LLVM_DEBUG(dbgs() << "********** Lowering br_unless **********\n"
                       "********** Function: "
                    << MF.getName() << '\n');

auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
  const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
  auto &MRI = MF.getRegInfo();

for (auto &MBB : MF) {
    for (auto MII = MBB.begin(); MII != MBB.end();) {
      MachineInstr *MI = &*MII++;
      if (MI->getOpcode() != WebAssembly::BR_UNLESS)
        continue;

// Attempt to invert the condition in place.
      if (MFI.isVRegStackified(Cond)) {
        assert(MRI.hasOneDef(Cond));
        MachineInstr *Def = MRI.getVRegDef(Cond);
        switch (Def->getOpcode()) {
          using namespace WebAssembly;
        case EQ_I32:
          Def->setDesc(TII.get(NE_I32));
          Inverted = true;
          break;
        case NE_I32:
          Def->setDesc(TII.get(EQ_I32));
          Inverted = true;
          break;
        case GT_S_I32:
          Def->setDesc(TII.get(LE_S_I32));
          Inverted = true;
          break;
        case GE_S_I32:
          Def->setDesc(TII.get(LT_S_I32));
          Inverted = true;
          break;
        case LT_S_I32:
          Def->setDesc(TII.get(GE_S_I32));
          Inverted = true;
          break;
        case LE_S_I32:
          Def->setDesc(TII.get(GT_S_I32));
          Inverted = true;
          break;
        case GT_U_I32:
          Def->setDesc(TII.get(LE_U_I32));
          Inverted = true;
          break;
        case GE_U_I32:
          Def->setDesc(TII.get(LT_U_I32));
          Inverted = true;
          break;
        case LT_U_I32:
          Def->setDesc(TII.get(GE_U_I32));
          Inverted = true;
          break;
        case LE_U_I32:
          Def->setDesc(TII.get(GT_U_I32));
          Inverted = true;
          break;
        case EQ_I64:
          Def->setDesc(TII.get(NE_I64));
          Inverted = true;
          break;
        case NE_I64:
          Def->setDesc(TII.get(EQ_I64));
          Inverted = true;
          break;
        case GT_S_I64:
          Def->setDesc(TII.get(LE_S_I64));
          Inverted = true;
          break;
        case GE_S_I64:
          Def->setDesc(TII.get(LT_S_I64));
          Inverted = true;
          break;
        case LT_S_I64:
          Def->setDesc(TII.get(GE_S_I64));
          Inverted = true;
          break;
        case LE_S_I64:
          Def->setDesc(TII.get(GT_S_I64));
          Inverted = true;
          break;
        case GT_U_I64:
          Def->setDesc(TII.get(LE_U_I64));
          Inverted = true;
          break;
        case GE_U_I64:
          Def->setDesc(TII.get(LT_U_I64));
          Inverted = true;
          break;
        case LT_U_I64:
          Def->setDesc(TII.get(GE_U_I64));
          Inverted = true;
          break;
        case LE_U_I64:
          Def->setDesc(TII.get(GT_U_I64));
          Inverted = true;
          break;
        case EQ_F32:
          Def->setDesc(TII.get(NE_F32));
          Inverted = true;
          break;
        case NE_F32:
          Def->setDesc(TII.get(EQ_F32));
          Inverted = true;
          break;
        case EQ_F64:
          Def->setDesc(TII.get(NE_F64));
          Inverted = true;
          break;
        case NE_F64:
          Def->setDesc(TII.get(EQ_F64));
          Inverted = true;
          break;
        case EQZ_I32: {
          // Invert an eqz by replacing it with its operand.
          Cond = Def->getOperand(1).getReg();
          Def->eraseFromParent();
          Inverted = true;
          break;
        }
        default:
          break;
        }
      }

// If we weren't able to invert the condition in place. Insert an
      // instruction to invert it.
      if (!Inverted) {
        Register Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
        BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
            .addReg(Cond);
        MFI.stackifyVReg(MRI, Tmp);
        Cond = Tmp;
        Inverted = true;
      }

// The br_unless condition has now been inverted. Insert a br_if and
      // delete the br_unless.
      assert(Inverted);
      BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
          .add(MI->getOperand(0))
          .addReg(Cond);
      MBB.erase(MI);
    }
  }

return true;
}

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Editing: WebAssemblyLowerBrUnless.cpp

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