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AsmParser
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Disassembler
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MCTargetDesc
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README.txt
(8.34 KB)
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TargetInfo
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WebAssembly.h
(4.05 KB)
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WebAssembly.td
(4.85 KB)
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WebAssemblyAddMissingPrototypes.cpp
(5.41 KB)
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WebAssemblyArgumentMove.cpp
(3.36 KB)
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WebAssemblyAsmPrinter.cpp
(16.09 KB)
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WebAssemblyAsmPrinter.h
(3.12 KB)
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WebAssemblyCFGSort.cpp
(15.94 KB)
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WebAssemblyCFGStackify.cpp
(55.56 KB)
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WebAssemblyDebugFixup.cpp
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WebAssemblyDebugValueManager.cpp
(1.77 KB)
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WebAssemblyDebugValueManager.h
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WebAssemblyExceptionInfo.cpp
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WebAssemblyExceptionInfo.h
(6.24 KB)
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WebAssemblyExplicitLocals.cpp
(15.04 KB)
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WebAssemblyFastISel.cpp
(40.39 KB)
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WebAssemblyFixBrTableDefaults.cpp
(5.81 KB)
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WebAssemblyFixFunctionBitcasts.cpp
(12.59 KB)
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WebAssemblyFixIrreducibleControlFlow.cpp
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WebAssemblyFrameLowering.cpp
(12.68 KB)
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WebAssemblyFrameLowering.h
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WebAssemblyISD.def
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WebAssemblyISelDAGToDAG.cpp
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WebAssemblyISelLowering.cpp
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WebAssemblyISelLowering.h
(5.85 KB)
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WebAssemblyInstrAtomics.td
(48.5 KB)
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WebAssemblyInstrBulkMemory.td
(2.84 KB)
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WebAssemblyInstrCall.td
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WebAssemblyInstrControl.td
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WebAssemblyInstrConv.td
(14.1 KB)
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WebAssemblyInstrFloat.td
(6.03 KB)
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WebAssemblyInstrFormats.td
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WebAssemblyInstrInfo.cpp
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WebAssemblyInstrInfo.h
(2.63 KB)
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WebAssemblyInstrInfo.td
(14.37 KB)
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WebAssemblyInstrInteger.td
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WebAssemblyInstrMemory.td
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WebAssemblyInstrRef.td
(1.15 KB)
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WebAssemblyInstrSIMD.td
(39.08 KB)
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WebAssemblyLateEHPrepare.cpp
(14.57 KB)
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WebAssemblyLowerBrUnless.cpp
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WebAssemblyLowerEmscriptenEHSjLj.cpp
(45.45 KB)
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WebAssemblyLowerGlobalDtors.cpp
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WebAssemblyMCInstLower.cpp
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WebAssemblyMCInstLower.h
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WebAssemblyMachineFunctionInfo.cpp
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WebAssemblyMachineFunctionInfo.h
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WebAssemblyMemIntrinsicResults.cpp
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WebAssemblyOptimizeLiveIntervals.cpp
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WebAssemblyOptimizeReturned.cpp
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WebAssemblyPeephole.cpp
(6.33 KB)
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WebAssemblyPrepareForLiveIntervals.cpp
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WebAssemblyRegColoring.cpp
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WebAssemblyRegNumbering.cpp
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WebAssemblyRegStackify.cpp
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WebAssemblyRegisterInfo.cpp
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WebAssemblyRegisterInfo.h
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WebAssemblyRegisterInfo.td
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WebAssemblyReplacePhysRegs.cpp
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WebAssemblyRuntimeLibcallSignatures.cpp
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WebAssemblyRuntimeLibcallSignatures.h
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WebAssemblySelectionDAGInfo.cpp
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WebAssemblySelectionDAGInfo.h
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WebAssemblySetP2AlignOperands.cpp
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WebAssemblySubtarget.cpp
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WebAssemblySubtarget.h
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WebAssemblyTargetMachine.cpp
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WebAssemblyTargetMachine.h
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WebAssemblyTargetObjectFile.cpp
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WebAssemblyTargetObjectFile.h
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WebAssemblyTargetTransformInfo.cpp
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WebAssemblyTargetTransformInfo.h
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WebAssemblyUtilities.cpp
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WebAssemblyUtilities.h
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known_gcc_test_failures.txt
(2.07 KB)
Editing: WebAssemblyTargetTransformInfo.cpp
//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// /// \file /// This file defines the WebAssembly-specific TargetTransformInfo /// implementation. /// //===----------------------------------------------------------------------===// #include "WebAssemblyTargetTransformInfo.h" #include "llvm/CodeGen/CostTable.h" #include "llvm/Support/Debug.h" using namespace llvm; #define DEBUG_TYPE "wasmtti" TargetTransformInfo::PopcntSupportKind WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const { assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); return TargetTransformInfo::PSK_FastHardware; } unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const { unsigned Result = BaseT::getNumberOfRegisters(ClassID); // For SIMD, use at least 16 registers, as a rough guess. bool Vector = (ClassID == 1); if (Vector) Result = std::max(Result, 16u); return Result; } unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const { if (Vector && getST()->hasSIMD128()) return 128; return 64; } unsigned WebAssemblyTTIImpl::getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args, const Instruction *CxtI) { unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost( Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo); if (auto *VTy = dyn_cast<VectorType>(Ty)) { switch (Opcode) { case Instruction::LShr: case Instruction::AShr: case Instruction::Shl: // SIMD128's shifts currently only accept a scalar shift count. For each // element, we'll need to extract, op, insert. The following is a rough // approxmation. if (Opd2Info != TTI::OK_UniformValue && Opd2Info != TTI::OK_UniformConstantValue) Cost = cast<FixedVectorType>(VTy)->getNumElements() * (TargetTransformInfo::TCC_Basic + getArithmeticInstrCost(Opcode, VTy->getElementType(), CostKind) + TargetTransformInfo::TCC_Basic); break; } } return Cost; } unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) { unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); // SIMD128's insert/extract currently only take constant indices. if (Index == -1u) return Cost + 25 * TargetTransformInfo::TCC_Expensive; return Cost; }
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