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..
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AsmParser
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Disassembler
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ImmutableGraph.h
(15.15 KB)
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MCTargetDesc
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TargetInfo
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X86.h
(7.41 KB)
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X86.td
(68.44 KB)
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X86AsmPrinter.cpp
(27.18 KB)
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X86AsmPrinter.h
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X86AvoidStoreForwardingBlocks.cpp
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X86AvoidTrailingCall.cpp
(4.91 KB)
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X86CallFrameOptimization.cpp
(23.07 KB)
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X86CallLowering.cpp
(17.62 KB)
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X86CallLowering.h
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X86CallingConv.cpp
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X86CallingConv.h
(1.09 KB)
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X86CallingConv.td
(46.15 KB)
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X86CmovConversion.cpp
(34.07 KB)
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X86CondBrFolding.cpp
(18.4 KB)
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X86DiscriminateMemOps.cpp
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X86DomainReassignment.cpp
(25.87 KB)
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X86EvexToVex.cpp
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X86ExpandPseudo.cpp
(16.95 KB)
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X86FastISel.cpp
(139.28 KB)
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X86FixupBWInsts.cpp
(18.09 KB)
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X86FixupLEAs.cpp
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X86FixupSetCC.cpp
(4.44 KB)
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X86FlagsCopyLowering.cpp
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X86FloatingPoint.cpp
(62.66 KB)
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X86FrameLowering.cpp
(138.71 KB)
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X86FrameLowering.h
(11.64 KB)
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X86GenRegisterBankInfo.def
(3.32 KB)
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X86ISelDAGToDAG.cpp
(208.37 KB)
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X86ISelLowering.cpp
(1.94 MB)
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X86ISelLowering.h
(60.88 KB)
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X86IndirectBranchTracking.cpp
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X86IndirectThunks.cpp
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X86InsertPrefetch.cpp
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X86InsertWait.cpp
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X86Instr3DNow.td
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X86InstrAMX.td
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X86InstrAVX512.td
(653.76 KB)
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X86InstrArithmetic.td
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X86InstrBuilder.h
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X86InstrCMovSetCC.td
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X86InstrCompiler.td
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X86InstrControl.td
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X86InstrExtension.td
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X86InstrFMA.td
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X86InstrFMA3Info.cpp
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X86InstrFMA3Info.h
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X86InstrFPStack.td
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X86InstrFoldTables.cpp
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X86InstrFoldTables.h
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X86InstrFormats.td
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X86InstrFragmentsSIMD.td
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X86InstrInfo.cpp
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X86InstrInfo.h
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X86InstrInfo.td
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X86InstrMMX.td
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X86InstrMPX.td
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X86InstrSGX.td
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X86InstrSSE.td
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X86InstrSVM.td
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X86InstrShiftRotate.td
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X86InstrSystem.td
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X86InstrTSX.td
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X86InstrVMX.td
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X86InstrVecCompiler.td
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X86InstrXOP.td
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X86InstructionSelector.cpp
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X86InterleavedAccess.cpp
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X86IntrinsicsInfo.h
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X86LegalizerInfo.cpp
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X86LegalizerInfo.h
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X86LoadValueInjectionLoadHardening.cpp
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X86LoadValueInjectionRetHardening.cpp
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X86MCInstLower.cpp
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X86MachineFunctionInfo.cpp
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X86MachineFunctionInfo.h
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X86MacroFusion.cpp
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X86MacroFusion.h
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X86OptimizeLEAs.cpp
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X86PadShortFunction.cpp
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X86PartialReduction.cpp
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X86PfmCounters.td
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X86RegisterBankInfo.cpp
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X86RegisterBankInfo.h
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X86RegisterBanks.td
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X86RegisterInfo.cpp
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X86RegisterInfo.h
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X86RegisterInfo.td
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X86SchedBroadwell.td
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X86SchedHaswell.td
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X86SchedPredicates.td
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X86SchedSandyBridge.td
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X86SchedSkylakeClient.td
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X86SchedSkylakeServer.td
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X86Schedule.td
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X86ScheduleAtom.td
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X86ScheduleBdVer2.td
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X86ScheduleBtVer2.td
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X86ScheduleSLM.td
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X86ScheduleZnver1.td
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X86ScheduleZnver2.td
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X86SelectionDAGInfo.cpp
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X86SelectionDAGInfo.h
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X86ShuffleDecodeConstantPool.cpp
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X86ShuffleDecodeConstantPool.h
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X86SpeculativeExecutionSideEffectSuppression.cpp
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X86SpeculativeLoadHardening.cpp
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X86Subtarget.cpp
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X86Subtarget.h
(32.08 KB)
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X86TargetMachine.cpp
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X86TargetMachine.h
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X86TargetObjectFile.cpp
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X86TargetObjectFile.h
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X86TargetTransformInfo.cpp
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X86TargetTransformInfo.h
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X86VZeroUpper.cpp
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X86WinAllocaExpander.cpp
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X86WinEHState.cpp
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Editing: X86FixupSetCC.cpp
//===---- X86FixupSetCC.cpp - optimize usage of LEA instructions ----------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file defines a pass that fixes zero-extension of setcc patterns. // X86 setcc instructions are modeled to have no input arguments, and a single // GR8 output argument. This is consistent with other similar instructions // (e.g. movb), but means it is impossible to directly generate a setcc into // the lower GR8 of a specified GR32. // This means that ISel must select (zext (setcc)) into something like // seta %al; movzbl %al, %eax. // Unfortunately, this can cause a stall due to the partial register write // performed by the setcc. Instead, we can use: // xor %eax, %eax; seta %al // This both avoids the stall, and encodes shorter. //===----------------------------------------------------------------------===// #include "X86.h" #include "X86InstrInfo.h" #include "X86Subtarget.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" using namespace llvm; #define DEBUG_TYPE "x86-fixup-setcc" STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted"); namespace { class X86FixupSetCCPass : public MachineFunctionPass { public: static char ID; X86FixupSetCCPass() : MachineFunctionPass(ID) {} StringRef getPassName() const override { return "X86 Fixup SetCC"; } bool runOnMachineFunction(MachineFunction &MF) override; private: MachineRegisterInfo *MRI = nullptr; const X86InstrInfo *TII = nullptr; enum { SearchBound = 16 }; }; } // end anonymous namespace char X86FixupSetCCPass::ID = 0; INITIALIZE_PASS(X86FixupSetCCPass, DEBUG_TYPE, DEBUG_TYPE, false, false) FunctionPass *llvm::createX86FixupSetCC() { return new X86FixupSetCCPass(); } bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) { bool Changed = false; MRI = &MF.getRegInfo(); TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); SmallVector<MachineInstr*, 4> ToErase; for (auto &MBB : MF) { MachineInstr *FlagsDefMI = nullptr; for (auto &MI : MBB) { // Remember the most recent preceding eflags defining instruction. if (MI.definesRegister(X86::EFLAGS)) FlagsDefMI = &MI; // Find a setcc that is used by a zext. // This doesn't have to be the only use, the transformation is safe // regardless. if (MI.getOpcode() != X86::SETCCr) continue; MachineInstr *ZExt = nullptr; for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg())) if (Use.getOpcode() == X86::MOVZX32rr8) ZExt = &Use; if (!ZExt) continue; if (!FlagsDefMI) continue; // We'd like to put something that clobbers eflags directly before // FlagsDefMI. This can't hurt anything after FlagsDefMI, because // it, itself, by definition, clobbers eflags. But it may happen that // FlagsDefMI also *uses* eflags, in which case the transformation is // invalid. if (FlagsDefMI->readsRegister(X86::EFLAGS)) continue; ++NumSubstZexts; Changed = true; // On 32-bit, we need to be careful to force an ABCD register. const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() ? &X86::GR32RegClass : &X86::GR32_ABCDRegClass; Register ZeroReg = MRI->createVirtualRegister(RC); Register InsertReg = MRI->createVirtualRegister(RC); // Initialize a register with 0. This must go before the eflags def BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0), ZeroReg); // X86 setcc only takes an output GR8, so fake a GR32 input by inserting // the setcc result into the low byte of the zeroed register. BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(), TII->get(X86::INSERT_SUBREG), InsertReg) .addReg(ZeroReg) .addReg(MI.getOperand(0).getReg()) .addImm(X86::sub_8bit); MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg); ToErase.push_back(ZExt); } } for (auto &I : ToErase) I->eraseFromParent(); return Changed; }
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