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📁 AsmParser
📁 Disassembler
📄 ImmutableGraph.h(15.15 KB)
📁 MCTargetDesc
📁 TargetInfo
📄 X86.h(7.41 KB)
📄 X86.td(68.44 KB)
📄 X86AsmPrinter.cpp(27.18 KB)
📄 X86AsmPrinter.h(5.96 KB)
📄 X86AvoidStoreForwardingBlocks.cpp(27.94 KB)
📄 X86AvoidTrailingCall.cpp(4.91 KB)
📄 X86CallFrameOptimization.cpp(23.07 KB)
📄 X86CallLowering.cpp(17.62 KB)
📄 X86CallLowering.h(1.74 KB)
📄 X86CallingConv.cpp(13.34 KB)
📄 X86CallingConv.h(1.09 KB)
📄 X86CallingConv.td(46.15 KB)
📄 X86CmovConversion.cpp(34.07 KB)
📄 X86CondBrFolding.cpp(18.4 KB)
📄 X86DiscriminateMemOps.cpp(7.11 KB)
📄 X86DomainReassignment.cpp(25.87 KB)
📄 X86EvexToVex.cpp(8.8 KB)
📄 X86ExpandPseudo.cpp(16.95 KB)
📄 X86FastISel.cpp(139.28 KB)
📄 X86FixupBWInsts.cpp(18.09 KB)
📄 X86FixupLEAs.cpp(24.44 KB)
📄 X86FixupSetCC.cpp(4.44 KB)
📄 X86FlagsCopyLowering.cpp(40.36 KB)
📄 X86FloatingPoint.cpp(62.66 KB)
📄 X86FrameLowering.cpp(138.71 KB)
📄 X86FrameLowering.h(11.64 KB)
📄 X86GenRegisterBankInfo.def(3.32 KB)
📄 X86ISelDAGToDAG.cpp(208.37 KB)
📄 X86ISelLowering.cpp(1.94 MB)
📄 X86ISelLowering.h(60.88 KB)
📄 X86IndirectBranchTracking.cpp(6.17 KB)
📄 X86IndirectThunks.cpp(9.78 KB)
📄 X86InsertPrefetch.cpp(9.64 KB)
📄 X86InsertWait.cpp(4.47 KB)
📄 X86Instr3DNow.td(5.24 KB)
📄 X86InstrAMX.td(5.6 KB)
📄 X86InstrAVX512.td(653.76 KB)
📄 X86InstrArithmetic.td(75.61 KB)
📄 X86InstrBuilder.h(8.45 KB)
📄 X86InstrCMovSetCC.td(5.76 KB)
📄 X86InstrCompiler.td(95.78 KB)
📄 X86InstrControl.td(20.53 KB)
📄 X86InstrExtension.td(11.64 KB)
📄 X86InstrFMA.td(33.23 KB)
📄 X86InstrFMA3Info.cpp(6.21 KB)
📄 X86InstrFMA3Info.h(3.25 KB)
📄 X86InstrFPStack.td(39.52 KB)
📄 X86InstrFoldTables.cpp(393.01 KB)
📄 X86InstrFoldTables.h(3.03 KB)
📄 X86InstrFormats.td(41.05 KB)
📄 X86InstrFragmentsSIMD.td(61.14 KB)
📄 X86InstrInfo.cpp(322.72 KB)
📄 X86InstrInfo.h(29.34 KB)
📄 X86InstrInfo.td(169.76 KB)
📄 X86InstrMMX.td(29.55 KB)
📄 X86InstrMPX.td(3.63 KB)
📄 X86InstrSGX.td(1.12 KB)
📄 X86InstrSSE.td(385.01 KB)
📄 X86InstrSVM.td(2.16 KB)
📄 X86InstrShiftRotate.td(49.56 KB)
📄 X86InstrSystem.td(34.03 KB)
📄 X86InstrTSX.td(2.1 KB)
📄 X86InstrVMX.td(3.53 KB)
📄 X86InstrVecCompiler.td(21.09 KB)
📄 X86InstrXOP.td(23.81 KB)
📄 X86InstructionSelector.cpp(61.11 KB)
📄 X86InterleavedAccess.cpp(32.7 KB)
📄 X86IntrinsicsInfo.h(73.96 KB)
📄 X86LegalizerInfo.cpp(15.6 KB)
📄 X86LegalizerInfo.h(1.65 KB)
📄 X86LoadValueInjectionLoadHardening.cpp(32.4 KB)
📄 X86LoadValueInjectionRetHardening.cpp(4.93 KB)
📄 X86MCInstLower.cpp(96.53 KB)
📄 X86MachineFunctionInfo.cpp(1.1 KB)
📄 X86MachineFunctionInfo.h(8.87 KB)
📄 X86MacroFusion.cpp(2.62 KB)
📄 X86MacroFusion.h(992 B)
📄 X86OptimizeLEAs.cpp(27.47 KB)
📄 X86PadShortFunction.cpp(7.33 KB)
📄 X86PartialReduction.cpp(15.46 KB)
📄 X86PfmCounters.td(10.18 KB)
📄 X86RegisterBankInfo.cpp(10.55 KB)
📄 X86RegisterBankInfo.h(2.87 KB)
📄 X86RegisterBanks.td(629 B)
📄 X86RegisterInfo.cpp(29 KB)
📄 X86RegisterInfo.h(5.61 KB)
📄 X86RegisterInfo.td(26.07 KB)
📄 X86SchedBroadwell.td(69.45 KB)
📄 X86SchedHaswell.td(73.96 KB)
📄 X86SchedPredicates.td(4.23 KB)
📄 X86SchedSandyBridge.td(50 KB)
📄 X86SchedSkylakeClient.td(74.65 KB)
📄 X86SchedSkylakeServer.td(113.85 KB)
📄 X86Schedule.td(36.9 KB)
📄 X86ScheduleAtom.td(38.26 KB)
📄 X86ScheduleBdVer2.td(56.78 KB)
📄 X86ScheduleBtVer2.td(46.98 KB)
📄 X86ScheduleSLM.td(22.91 KB)
📄 X86ScheduleZnver1.td(48.97 KB)
📄 X86ScheduleZnver2.td(48.12 KB)
📄 X86SelectionDAGInfo.cpp(12.02 KB)
📄 X86SelectionDAGInfo.h(1.8 KB)
📄 X86ShuffleDecodeConstantPool.cpp(11.22 KB)
📄 X86ShuffleDecodeConstantPool.h(2.13 KB)
📄 X86SpeculativeExecutionSideEffectSuppression.cpp(6.97 KB)
📄 X86SpeculativeLoadHardening.cpp(93.16 KB)
📄 X86Subtarget.cpp(13.25 KB)
📄 X86Subtarget.h(32.08 KB)
📄 X86TargetMachine.cpp(18.88 KB)
📄 X86TargetMachine.h(2.04 KB)
📄 X86TargetObjectFile.cpp(2.61 KB)
📄 X86TargetObjectFile.h(2.13 KB)
📄 X86TargetTransformInfo.cpp(189.14 KB)
📄 X86TargetTransformInfo.h(9.63 KB)
📄 X86VZeroUpper.cpp(12.59 KB)
📄 X86WinAllocaExpander.cpp(9.54 KB)
📄 X86WinEHState.cpp(28.97 KB)

Editing: X86GenRegisterBankInfo.def

//===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
/// \file
/// This file defines all the static objects used by X86RegisterBankInfo.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//

#ifdef GET_TARGET_REGBANK_INFO_IMPL
RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
    /* StartIdx, Length, RegBank */
    // GPR value
    {0, 8, X86::GPRRegBank},   // :0
    {0, 16, X86::GPRRegBank},  // :1
    {0, 32, X86::GPRRegBank},  // :2
    {0, 64, X86::GPRRegBank},  // :3
    // FR32/64 , xmm registers
    {0, 32, X86::VECRRegBank},  // :4
    {0, 64, X86::VECRRegBank},  // :5
    // VR128/256/512
    {0, 128, X86::VECRRegBank}, // :6
    {0, 256, X86::VECRRegBank}, // :7
    {0, 512, X86::VECRRegBank}, // :8   
};
#endif // GET_TARGET_REGBANK_INFO_IMPL

#ifdef GET_TARGET_REGBANK_INFO_CLASS
enum PartialMappingIdx {
  PMI_None = -1,
  PMI_GPR8,
  PMI_GPR16,
  PMI_GPR32,
  PMI_GPR64,
  PMI_FP32,
  PMI_FP64,
  PMI_VEC128,
  PMI_VEC256,
  PMI_VEC512
};
#endif // GET_TARGET_REGBANK_INFO_CLASS

#ifdef GET_TARGET_REGBANK_INFO_IMPL
#define INSTR_3OP(INFO) INFO, INFO, INFO,
#define BREAKDOWN(INDEX, NUM)                                                  \
  { &X86GenRegisterBankInfo::PartMappings[INDEX], NUM }
// ValueMappings.
RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{
    /* BreakDown, NumBreakDowns */
    // 3-operands instructions (all binary operations should end up with one of
    // those mapping).
    INSTR_3OP(BREAKDOWN(PMI_GPR8, 1))  // 0: GPR_8
    INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16
    INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
    INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64    
    INSTR_3OP(BREAKDOWN(PMI_FP32, 1))   // 12: Fp32
    INSTR_3OP(BREAKDOWN(PMI_FP64, 1))   // 15: Fp64
    INSTR_3OP(BREAKDOWN(PMI_VEC128, 1)) // 18: Vec128
    INSTR_3OP(BREAKDOWN(PMI_VEC256, 1)) // 21: Vec256
    INSTR_3OP(BREAKDOWN(PMI_VEC512, 1)) // 24: Vec512    
};
#undef INSTR_3OP
#undef BREAKDOWN
#endif // GET_TARGET_REGBANK_INFO_IMPL

#ifdef GET_TARGET_REGBANK_INFO_CLASS
enum ValueMappingIdx {
  VMI_None = -1,
  VMI_3OpsGpr8Idx =  PMI_GPR8  * 3,
  VMI_3OpsGpr16Idx = PMI_GPR16 * 3,
  VMI_3OpsGpr32Idx = PMI_GPR32 * 3,
  VMI_3OpsGpr64Idx = PMI_GPR64 * 3,  
  VMI_3OpsFp32Idx = PMI_FP32 * 3,
  VMI_3OpsFp64Idx = PMI_FP64 * 3,
  VMI_3OpsVec128Idx = PMI_VEC128 * 3,
  VMI_3OpsVec256Idx = PMI_VEC256 * 3,
  VMI_3OpsVec512Idx = PMI_VEC512 * 3,
};
#undef GET_TARGET_REGBANK_INFO_CLASS
#endif // GET_TARGET_REGBANK_INFO_CLASS

#ifdef GET_TARGET_REGBANK_INFO_IMPL
#undef GET_TARGET_REGBANK_INFO_IMPL
const RegisterBankInfo::ValueMapping *
X86GenRegisterBankInfo::getValueMapping(PartialMappingIdx Idx,
                                        unsigned NumOperands) {
  
  // We can use VMI_3Ops Mapping for all the cases.
  if (NumOperands <= 3 && (Idx >= PMI_GPR8 && Idx <= PMI_VEC512))
    return &ValMappings[(unsigned)Idx * 3];
  
  llvm_unreachable("Unsupported PartialMappingIdx.");
}

#endif // GET_TARGET_REGBANK_INFO_IMPL

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Editing: X86GenRegisterBankInfo.def

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