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..
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AsmParser
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Disassembler
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ImmutableGraph.h
(15.15 KB)
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MCTargetDesc
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TargetInfo
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X86.h
(7.41 KB)
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X86.td
(68.44 KB)
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X86AsmPrinter.cpp
(27.18 KB)
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X86AsmPrinter.h
(5.96 KB)
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X86AvoidStoreForwardingBlocks.cpp
(27.94 KB)
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X86AvoidTrailingCall.cpp
(4.91 KB)
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X86CallFrameOptimization.cpp
(23.07 KB)
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X86CallLowering.cpp
(17.62 KB)
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X86CallLowering.h
(1.74 KB)
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X86CallingConv.cpp
(13.34 KB)
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X86CallingConv.h
(1.09 KB)
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X86CallingConv.td
(46.15 KB)
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X86CmovConversion.cpp
(34.07 KB)
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X86CondBrFolding.cpp
(18.4 KB)
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X86DiscriminateMemOps.cpp
(7.11 KB)
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X86DomainReassignment.cpp
(25.87 KB)
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X86EvexToVex.cpp
(8.8 KB)
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X86ExpandPseudo.cpp
(16.95 KB)
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X86FastISel.cpp
(139.28 KB)
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X86FixupBWInsts.cpp
(18.09 KB)
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X86FixupLEAs.cpp
(24.44 KB)
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X86FixupSetCC.cpp
(4.44 KB)
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X86FlagsCopyLowering.cpp
(40.36 KB)
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X86FloatingPoint.cpp
(62.66 KB)
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X86FrameLowering.cpp
(138.71 KB)
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X86FrameLowering.h
(11.64 KB)
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X86GenRegisterBankInfo.def
(3.32 KB)
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X86ISelDAGToDAG.cpp
(208.37 KB)
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X86ISelLowering.cpp
(1.94 MB)
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X86ISelLowering.h
(60.88 KB)
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X86IndirectBranchTracking.cpp
(6.17 KB)
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X86IndirectThunks.cpp
(9.78 KB)
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X86InsertPrefetch.cpp
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X86InsertWait.cpp
(4.47 KB)
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X86Instr3DNow.td
(5.24 KB)
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X86InstrAMX.td
(5.6 KB)
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X86InstrAVX512.td
(653.76 KB)
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X86InstrArithmetic.td
(75.61 KB)
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X86InstrBuilder.h
(8.45 KB)
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X86InstrCMovSetCC.td
(5.76 KB)
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X86InstrCompiler.td
(95.78 KB)
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X86InstrControl.td
(20.53 KB)
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X86InstrExtension.td
(11.64 KB)
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X86InstrFMA.td
(33.23 KB)
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X86InstrFMA3Info.cpp
(6.21 KB)
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X86InstrFMA3Info.h
(3.25 KB)
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X86InstrFPStack.td
(39.52 KB)
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X86InstrFoldTables.cpp
(393.01 KB)
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X86InstrFoldTables.h
(3.03 KB)
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X86InstrFormats.td
(41.05 KB)
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X86InstrFragmentsSIMD.td
(61.14 KB)
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X86InstrInfo.cpp
(322.72 KB)
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X86InstrInfo.h
(29.34 KB)
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X86InstrInfo.td
(169.76 KB)
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X86InstrMMX.td
(29.55 KB)
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X86InstrMPX.td
(3.63 KB)
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X86InstrSGX.td
(1.12 KB)
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X86InstrSSE.td
(385.01 KB)
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X86InstrSVM.td
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X86InstrShiftRotate.td
(49.56 KB)
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X86InstrSystem.td
(34.03 KB)
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X86InstrTSX.td
(2.1 KB)
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X86InstrVMX.td
(3.53 KB)
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X86InstrVecCompiler.td
(21.09 KB)
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X86InstrXOP.td
(23.81 KB)
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X86InstructionSelector.cpp
(61.11 KB)
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X86InterleavedAccess.cpp
(32.7 KB)
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X86IntrinsicsInfo.h
(73.96 KB)
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X86LegalizerInfo.cpp
(15.6 KB)
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X86LegalizerInfo.h
(1.65 KB)
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X86LoadValueInjectionLoadHardening.cpp
(32.4 KB)
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X86LoadValueInjectionRetHardening.cpp
(4.93 KB)
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X86MCInstLower.cpp
(96.53 KB)
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X86MachineFunctionInfo.cpp
(1.1 KB)
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X86MachineFunctionInfo.h
(8.87 KB)
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X86MacroFusion.cpp
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X86MacroFusion.h
(992 B)
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X86OptimizeLEAs.cpp
(27.47 KB)
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X86PadShortFunction.cpp
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X86PartialReduction.cpp
(15.46 KB)
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X86PfmCounters.td
(10.18 KB)
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X86RegisterBankInfo.cpp
(10.55 KB)
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X86RegisterBankInfo.h
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X86RegisterBanks.td
(629 B)
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X86RegisterInfo.cpp
(29 KB)
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X86RegisterInfo.h
(5.61 KB)
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X86RegisterInfo.td
(26.07 KB)
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X86SchedBroadwell.td
(69.45 KB)
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X86SchedHaswell.td
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X86SchedPredicates.td
(4.23 KB)
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X86SchedSandyBridge.td
(50 KB)
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X86SchedSkylakeClient.td
(74.65 KB)
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X86SchedSkylakeServer.td
(113.85 KB)
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X86Schedule.td
(36.9 KB)
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X86ScheduleAtom.td
(38.26 KB)
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X86ScheduleBdVer2.td
(56.78 KB)
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X86ScheduleBtVer2.td
(46.98 KB)
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X86ScheduleSLM.td
(22.91 KB)
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X86ScheduleZnver1.td
(48.97 KB)
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X86ScheduleZnver2.td
(48.12 KB)
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X86SelectionDAGInfo.cpp
(12.02 KB)
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X86SelectionDAGInfo.h
(1.8 KB)
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X86ShuffleDecodeConstantPool.cpp
(11.22 KB)
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X86ShuffleDecodeConstantPool.h
(2.13 KB)
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X86SpeculativeExecutionSideEffectSuppression.cpp
(6.97 KB)
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X86SpeculativeLoadHardening.cpp
(93.16 KB)
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X86Subtarget.cpp
(13.25 KB)
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X86Subtarget.h
(32.08 KB)
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X86TargetMachine.cpp
(18.88 KB)
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X86TargetMachine.h
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X86TargetObjectFile.cpp
(2.61 KB)
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X86TargetObjectFile.h
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X86TargetTransformInfo.cpp
(189.14 KB)
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X86TargetTransformInfo.h
(9.63 KB)
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X86VZeroUpper.cpp
(12.59 KB)
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X86WinAllocaExpander.cpp
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X86WinEHState.cpp
(28.97 KB)
Editing: X86InstrMPX.td
//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file describes the X86 MPX instruction set, defining the // instructions, and properties of the instructions which are needed for code // generation, machine code emission, and analysis. // //===----------------------------------------------------------------------===// // FIXME: Investigate a better scheduler class if MPX is ever used inside LLVM. let SchedRW = [WriteSystem] in { multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> { def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}", []>, Requires<[Not64BitMode]>; def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}", []>, Requires<[In64BitMode]>; } defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS; multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> { def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2), OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, Requires<[Not64BitMode]>; def 64rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, anymem:$src2), OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, Requires<[In64BitMode]>; def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2), OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, Requires<[Not64BitMode]>; def 64rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2), OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>, Requires<[In64BitMode]>; } defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable; defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable; defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable; def BNDMOVrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, NotMemoryFoldable; let mayLoad = 1 in { def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, Requires<[Not64BitMode]>, NotMemoryFoldable; def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, Requires<[In64BitMode]>, NotMemoryFoldable; } let isCodeGenOnly = 1, ForceDisassemble = 1 in def BNDMOVrr_REV : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, NotMemoryFoldable; let mayStore = 1 in { def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, Requires<[Not64BitMode]>, NotMemoryFoldable; def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src), "bndmov\t{$src, $dst|$dst, $src}", []>, PD, Requires<[In64BitMode]>, NotMemoryFoldable; def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src), "bndstx\t{$src, $dst|$dst, $src}", []>, PS; } let mayLoad = 1 in def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src), "bndldx\t{$src, $dst|$dst, $src}", []>, PS; } // SchedRW
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