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📄 AArch64.cpp(29.01 KB)
📄 AArch64.h(6.99 KB)
📄 AMDGPU.cpp(15.27 KB)
📄 AMDGPU.h(11.06 KB)
📄 ARC.cpp(857 B)
📄 ARC.h(2.44 KB)
📄 ARM.cpp(42.48 KB)
📄 ARM.h(8.67 KB)
📄 AVR.cpp(12.02 KB)
📄 AVR.h(5.74 KB)
📄 BPF.cpp(1.75 KB)
📄 BPF.h(3.11 KB)
📄 Hexagon.cpp(7.02 KB)
📄 Hexagon.h(4.49 KB)
📄 Lanai.cpp(2.31 KB)
📄 Lanai.h(3.09 KB)
📄 Le64.cpp(1.38 KB)
📄 Le64.h(1.99 KB)
📄 MSP430.cpp(1.14 KB)
📄 MSP430.h(2.99 KB)
📄 Mips.cpp(9.62 KB)
📄 Mips.h(13.84 KB)
📄 NVPTX.cpp(8.97 KB)
📄 NVPTX.h(5.28 KB)
📄 OSTargets.cpp(7.11 KB)
📄 OSTargets.h(29.36 KB)
📄 PNaCl.cpp(1001 B)
📄 PNaCl.h(2.78 KB)
📄 PPC.cpp(21.1 KB)
📄 PPC.h(17.89 KB)
📄 RISCV.cpp(6.88 KB)
📄 RISCV.h(4.14 KB)
📄 SPIR.cpp(1.2 KB)
📄 SPIR.h(4.54 KB)
📄 Sparc.cpp(9.86 KB)
📄 Sparc.h(7.06 KB)
📄 SystemZ.cpp(5.16 KB)
📄 SystemZ.h(4.88 KB)
📄 TCE.cpp(1.17 KB)
📄 TCE.h(3.99 KB)
📄 VE.cpp(1.43 KB)
📄 VE.h(5.14 KB)
📄 WebAssembly.cpp(8.19 KB)
📄 WebAssembly.h(5.6 KB)
📄 X86.cpp(48.61 KB)
📄 X86.h(27.36 KB)
📄 XCore.cpp(1.42 KB)
📄 XCore.h(2.61 KB)

Editing: XCore.h

//===--- XCore.h - Declare XCore target feature support ---------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares XCore TargetInfo objects.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XCORE_H
#define LLVM_CLANG_LIB_BASIC_TARGETS_XCORE_H

#include "clang/Basic/TargetInfo.h"
#include "clang/Basic/TargetOptions.h"
#include "llvm/ADT/Triple.h"
#include "llvm/Support/Compiler.h"

namespace clang {
namespace targets {

class LLVM_LIBRARY_VISIBILITY XCoreTargetInfo : public TargetInfo {
  static const Builtin::Info BuiltinInfo[];

public:
  XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
      : TargetInfo(Triple) {
    NoAsmVariants = true;
    LongLongAlign = 32;
    SuitableAlign = 32;
    DoubleAlign = LongDoubleAlign = 32;
    SizeType = UnsignedInt;
    PtrDiffType = SignedInt;
    IntPtrType = SignedInt;
    WCharType = UnsignedChar;
    WIntType = UnsignedInt;
    UseZeroLengthBitfieldAlignment = true;
    resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
                    "-f64:32-a:0:32-n32");
  }

void getTargetDefines(const LangOptions &Opts,
                        MacroBuilder &Builder) const override;

ArrayRef<Builtin::Info> getTargetBuiltins() const override;

BuiltinVaListKind getBuiltinVaListKind() const override {
    return TargetInfo::VoidPtrBuiltinVaList;
  }

const char *getClobbers() const override { return ""; }

ArrayRef<const char *> getGCCRegNames() const override {
    static const char *const GCCRegNames[] = {
        "r0", "r1", "r2",  "r3",  "r4", "r5", "r6", "r7",
        "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
    };
    return llvm::makeArrayRef(GCCRegNames);
  }

ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
    return None;
  }

bool validateAsmConstraint(const char *&Name,
                             TargetInfo::ConstraintInfo &Info) const override {
    return false;
  }

int getEHDataRegisterNumber(unsigned RegNo) const override {
    // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
    return (RegNo < 2) ? RegNo : -1;
  }

bool allowsLargerPreferedTypeAlignment() const override { return false; }

bool hasExtIntType() const override { return true; }
};
} // namespace targets
} // namespace clang
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XCORE_H

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Editing: XCore.h

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