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📁 ..
📁 Disassembler
📁 MCTargetDesc
📁 TargetInfo
📄 XCore.h(1.13 KB)
📄 XCore.td(1.7 KB)
📄 XCoreAsmPrinter.cpp(10.24 KB)
📄 XCoreCallingConv.td(1.62 KB)
📄 XCoreFrameLowering.cpp(24.02 KB)
📄 XCoreFrameLowering.h(2.35 KB)
📄 XCoreFrameToArgsOffsetElim.cpp(2.27 KB)
📄 XCoreISelDAGToDAG.cpp(10.31 KB)
📄 XCoreISelLowering.cpp(75.02 KB)
📄 XCoreISelLowering.h(8.8 KB)
📄 XCoreInstrFormats.td(8.66 KB)
📄 XCoreInstrInfo.cpp(15.16 KB)
📄 XCoreInstrInfo.h(4.02 KB)
📄 XCoreInstrInfo.td(50.2 KB)
📄 XCoreLowerThreadLocal.cpp(8.17 KB)
📄 XCoreMCInstLower.cpp(3.79 KB)
📄 XCoreMCInstLower.h(1.24 KB)
📄 XCoreMachineFunctionInfo.cpp(2.93 KB)
📄 XCoreMachineFunctionInfo.h(2.89 KB)
📄 XCoreRegisterInfo.cpp(10.28 KB)
📄 XCoreRegisterInfo.h(1.59 KB)
📄 XCoreRegisterInfo.td(1.88 KB)
📄 XCoreSelectionDAGInfo.cpp(2.03 KB)
📄 XCoreSelectionDAGInfo.h(1.18 KB)
📄 XCoreSubtarget.cpp(1.07 KB)
📄 XCoreSubtarget.h(2.1 KB)
📄 XCoreTargetMachine.cpp(3.53 KB)
📄 XCoreTargetMachine.h(1.81 KB)
📄 XCoreTargetObjectFile.cpp(6.47 KB)
📄 XCoreTargetObjectFile.h(1.42 KB)
📄 XCoreTargetStreamer.h(887 B)
📄 XCoreTargetTransformInfo.h(1.76 KB)

Editing: XCoreInstrInfo.h

//===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains the XCore implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
#define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H

#include "XCoreRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"

#define GET_INSTRINFO_HEADER
#include "XCoreGenInstrInfo.inc"

namespace llvm {

class XCoreInstrInfo : public XCoreGenInstrInfo {
  const XCoreRegisterInfo RI;
  virtual void anchor();
public:
  XCoreInstrInfo();

/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  /// such, whenever a client has an instance of instruction info, it should
  /// always be able to get register info as well (through this method).
  ///
  const TargetRegisterInfo &getRegisterInfo() const { return RI; }

/// isLoadFromStackSlot - If the specified machine instruction is a direct
  /// load from a stack slot, return the virtual or physical register number of
  /// the destination along with the FrameIndex of the loaded stack slot.  If
  /// not, return 0.  This predicate must return 0 if the instruction has
  /// any side effects other than loading from the stack slot.
  unsigned isLoadFromStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;

/// isStoreToStackSlot - If the specified machine instruction is a direct
  /// store to a stack slot, return the virtual or physical register number of
  /// the source reg along with the FrameIndex of the loaded stack slot.  If
  /// not, return 0.  This predicate must return 0 if the instruction has
  /// any side effects other than storing to the stack slot.
  unsigned isStoreToStackSlot(const MachineInstr &MI,
                              int &FrameIndex) const override;

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                     MachineBasicBlock *&FBB,
                     SmallVectorImpl<MachineOperand> &Cond,
                     bool AllowModify) const override;

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                        const DebugLoc &DL,
                        int *BytesAdded = nullptr) const override;

unsigned removeBranch(MachineBasicBlock &MBB,
                        int *BytesRemoved = nullptr) const override;

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                   const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
                   bool KillSrc) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           Register SrcReg, bool isKill, int FrameIndex,
                           const TargetRegisterClass *RC,
                           const TargetRegisterInfo *TRI) const override;

void loadRegFromStackSlot(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI,
                            Register DestReg, int FrameIndex,
                            const TargetRegisterClass *RC,
                            const TargetRegisterInfo *TRI) const override;

bool reverseBranchCondition(
                          SmallVectorImpl<MachineOperand> &Cond) const override;

// Emit code before MBBI to load immediate value into physical register Reg.
  // Returns an iterator to the new instruction.
  MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MI,
                                            unsigned Reg, uint64_t Value) const;
};

}

#endif

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Editing: XCoreInstrInfo.h

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