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TargetInfo
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XCore.h
(1.13 KB)
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XCore.td
(1.7 KB)
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XCoreAsmPrinter.cpp
(10.24 KB)
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XCoreCallingConv.td
(1.62 KB)
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XCoreFrameLowering.cpp
(24.02 KB)
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XCoreFrameLowering.h
(2.35 KB)
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XCoreFrameToArgsOffsetElim.cpp
(2.27 KB)
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XCoreISelDAGToDAG.cpp
(10.31 KB)
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XCoreISelLowering.cpp
(75.02 KB)
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XCoreISelLowering.h
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XCoreInstrFormats.td
(8.66 KB)
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XCoreInstrInfo.cpp
(15.16 KB)
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XCoreInstrInfo.h
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XCoreInstrInfo.td
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XCoreLowerThreadLocal.cpp
(8.17 KB)
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XCoreMCInstLower.cpp
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XCoreMCInstLower.h
(1.24 KB)
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XCoreMachineFunctionInfo.cpp
(2.93 KB)
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XCoreMachineFunctionInfo.h
(2.89 KB)
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XCoreRegisterInfo.cpp
(10.28 KB)
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XCoreRegisterInfo.h
(1.59 KB)
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XCoreRegisterInfo.td
(1.88 KB)
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XCoreSelectionDAGInfo.cpp
(2.03 KB)
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XCoreSelectionDAGInfo.h
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XCoreSubtarget.cpp
(1.07 KB)
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XCoreSubtarget.h
(2.1 KB)
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XCoreTargetMachine.cpp
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XCoreTargetMachine.h
(1.81 KB)
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XCoreTargetObjectFile.cpp
(6.47 KB)
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XCoreTargetObjectFile.h
(1.42 KB)
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XCoreTargetStreamer.h
(887 B)
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XCoreTargetTransformInfo.h
(1.76 KB)
Editing: XCoreMachineFunctionInfo.cpp
//===-- XCoreMachineFunctionInfo.cpp - XCore machine function info --------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "XCoreMachineFunctionInfo.h" #include "XCoreInstrInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/Function.h" using namespace llvm; void XCoreFunctionInfo::anchor() { } bool XCoreFunctionInfo::isLargeFrame(const MachineFunction &MF) const { if (CachedEStackSize == -1) { CachedEStackSize = MF.getFrameInfo().estimateStackSize(MF); } // isLargeFrame() is used when deciding if spill slots should be added to // allow eliminateFrameIndex() to scavenge registers. // This is only required when there is no FP and offsets are greater than // ~256KB (~64Kwords). Thus only for code run on the emulator! // // The arbitrary value of 0xf000 allows frames of up to ~240KB before spill // slots are added for the use of eliminateFrameIndex() register scavenging. // For frames less than 240KB, it is assumed that there will be less than // 16KB of function arguments. return CachedEStackSize > 0xf000; } int XCoreFunctionInfo::createLRSpillSlot(MachineFunction &MF) { if (LRSpillSlotSet) { return LRSpillSlot; } const TargetRegisterClass &RC = XCore::GRRegsRegClass; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); if (! MF.getFunction().isVarArg()) { // A fixed offset of 0 allows us to save / restore LR using entsp / retsp. LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true); } else { LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); } LRSpillSlotSet = true; return LRSpillSlot; } int XCoreFunctionInfo::createFPSpillSlot(MachineFunction &MF) { if (FPSpillSlotSet) { return FPSpillSlot; } const TargetRegisterClass &RC = XCore::GRRegsRegClass; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); FPSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); FPSpillSlotSet = true; return FPSpillSlot; } const int* XCoreFunctionInfo::createEHSpillSlot(MachineFunction &MF) { if (EHSpillSlotSet) { return EHSpillSlot; } const TargetRegisterClass &RC = XCore::GRRegsRegClass; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned Size = TRI.getSpillSize(RC); Align Alignment = TRI.getSpillAlign(RC); EHSpillSlot[0] = MFI.CreateStackObject(Size, Alignment, true); EHSpillSlot[1] = MFI.CreateStackObject(Size, Alignment, true); EHSpillSlotSet = true; return EHSpillSlot; }
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