File Manager

003 File Manager

Current Path: /usr/src/contrib/llvm-project/llvm/lib/Target/XCore

usr / src / contrib / llvm-project / llvm / lib / Target / XCore /

📁 ..
📁 Disassembler
📁 MCTargetDesc
📁 TargetInfo
📄 XCore.h(1.13 KB)
📄 XCore.td(1.7 KB)
📄 XCoreAsmPrinter.cpp(10.24 KB)
📄 XCoreCallingConv.td(1.62 KB)
📄 XCoreFrameLowering.cpp(24.02 KB)
📄 XCoreFrameLowering.h(2.35 KB)
📄 XCoreFrameToArgsOffsetElim.cpp(2.27 KB)
📄 XCoreISelDAGToDAG.cpp(10.31 KB)
📄 XCoreISelLowering.cpp(75.02 KB)
📄 XCoreISelLowering.h(8.8 KB)
📄 XCoreInstrFormats.td(8.66 KB)
📄 XCoreInstrInfo.cpp(15.16 KB)
📄 XCoreInstrInfo.h(4.02 KB)
📄 XCoreInstrInfo.td(50.2 KB)
📄 XCoreLowerThreadLocal.cpp(8.17 KB)
📄 XCoreMCInstLower.cpp(3.79 KB)
📄 XCoreMCInstLower.h(1.24 KB)
📄 XCoreMachineFunctionInfo.cpp(2.93 KB)
📄 XCoreMachineFunctionInfo.h(2.89 KB)
📄 XCoreRegisterInfo.cpp(10.28 KB)
📄 XCoreRegisterInfo.h(1.59 KB)
📄 XCoreRegisterInfo.td(1.88 KB)
📄 XCoreSelectionDAGInfo.cpp(2.03 KB)
📄 XCoreSelectionDAGInfo.h(1.18 KB)
📄 XCoreSubtarget.cpp(1.07 KB)
📄 XCoreSubtarget.h(2.1 KB)
📄 XCoreTargetMachine.cpp(3.53 KB)
📄 XCoreTargetMachine.h(1.81 KB)
📄 XCoreTargetObjectFile.cpp(6.47 KB)
📄 XCoreTargetObjectFile.h(1.42 KB)
📄 XCoreTargetStreamer.h(887 B)
📄 XCoreTargetTransformInfo.h(1.76 KB)

Editing: XCoreRegisterInfo.td

//===-- XCoreRegisterInfo.td - XCore Register defs ---------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
//  Declarations that describe the XCore register file
//===----------------------------------------------------------------------===//

class XCoreReg<string n> : Register<n> {
  field bits<4> Num;
  let Namespace = "XCore";
}

// Registers are identified with 4-bit ID numbers.
// Ri - 32-bit integer registers
class Ri<bits<4> num, string n> : XCoreReg<n> {
  let Num = num;
}

// CPU registers
def R0  : Ri< 0, "r0">, DwarfRegNum<[0]>;
def R1  : Ri< 1, "r1">, DwarfRegNum<[1]>;
def R2  : Ri< 2, "r2">, DwarfRegNum<[2]>;
def R3  : Ri< 3, "r3">, DwarfRegNum<[3]>;
def R4  : Ri< 4, "r4">, DwarfRegNum<[4]>;
def R5  : Ri< 5, "r5">, DwarfRegNum<[5]>;
def R6  : Ri< 6, "r6">, DwarfRegNum<[6]>;
def R7  : Ri< 7, "r7">, DwarfRegNum<[7]>;
def R8  : Ri< 8, "r8">, DwarfRegNum<[8]>;
def R9  : Ri< 9, "r9">, DwarfRegNum<[9]>;
def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
def CP : Ri<12, "cp">, DwarfRegNum<[12]>;
def DP : Ri<13, "dp">, DwarfRegNum<[13]>;
def SP : Ri<14, "sp">, DwarfRegNum<[14]>;
def LR : Ri<15, "lr">, DwarfRegNum<[15]>;

// Register classes.
//
def GRRegs : RegisterClass<"XCore", [i32], 32,
  // Return values and arguments
  (add R0, R1, R2, R3,
  // Callee save
  R4, R5, R6, R7, R8, R9, R10,
  // Not preserved across procedure calls
  R11)>;

// Reserved
def RRegs : RegisterClass<"XCore", [i32], 32,
  (add R0, R1, R2, R3,
   R4, R5, R6, R7, R8, R9, R10,
   R11, CP, DP, SP, LR)> {
  let isAllocatable = 0;
}

003 File Manager

Editing: XCoreRegisterInfo.td

Upload File

Create Folder