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adpll.txt
(1.4 KB)
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apll.txt
(1.78 KB)
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autoidle.txt
(1.2 KB)
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clockdomain.txt
(880 B)
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composite.txt
(1.59 KB)
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davinci
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divider.txt
(3.68 KB)
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dpll.txt
(2.86 KB)
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dra7-atl.txt
(2.81 KB)
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fapll.txt
(1.04 KB)
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fixed-factor-clock.txt
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gate.txt
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interface.txt
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mux.txt
(2.58 KB)
Editing: adpll.txt
Binding for Texas Instruments ADPLL clock. Binding status: Unstable - ABI compatibility may be broken in the future This binding uses the common clock binding[1]. It assumes a register-mapped ADPLL with two to three selectable input clocks and three to four children. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt Required properties: - compatible : shall be one of "ti,dm814-adpll-s-clock" or "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL - #clock-cells : from common clock binding; shall be set to 1. - clocks : link phandles of parent clocks clkinp and clkinpulow, note that the adpll-s-clock also has an optional clkinphif - reg : address and length of the register set for controlling the ADPLL. Examples: adpll_mpu_ck: adpll@40 { #clock-cells = <1>; compatible = "ti,dm814-adpll-s-clock"; reg = <0x40 0x40>; clocks = <&devosc_ck &devosc_ck &devosc_ck>; clock-names = "clkinp", "clkinpulow", "clkinphif"; clock-output-names = "481c5040.adpll.dcoclkldo", "481c5040.adpll.clkout", "481c5040.adpll.clkoutx2", "481c5040.adpll.clkouthif"; }; adpll_dsp_ck: adpll@80 { #clock-cells = <1>; compatible = "ti,dm814-adpll-lj-clock"; reg = <0x80 0x30>; clocks = <&devosc_ck &devosc_ck>; clock-names = "clkinp", "clkinpulow"; clock-output-names = "481c5080.adpll.dcoclkldo", "481c5080.adpll.clkout", "481c5080.adpll.clkoutldo"; };
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