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usr / src / sys / contrib / device-tree / Bindings / fpga /

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📄 altera-fpga2sdram-bridge.txt(353 B)
📄 altera-freeze-bridge.txt(697 B)
📄 altera-hps2fpga-bridge.txt(1.02 KB)
📄 altera-passive-serial.txt(988 B)
📄 altera-pr-ip.txt(276 B)
📄 altera-socfpga-a10-fpga-mgr.txt(629 B)
📄 altera-socfpga-fpga-mgr.txt(533 B)
📄 fpga-bridge.txt(367 B)
📄 fpga-region.txt(17.25 KB)
📄 intel-stratix10-soc-fpga-mgr.txt(372 B)
📄 lattice-ice40-fpga-mgr.txt(729 B)
📄 lattice-machxo2-spi.txt(656 B)
📄 xilinx-pr-decoupler.txt(1.12 KB)
📄 xilinx-slave-serial.txt(1.62 KB)
📄 xilinx-zynq-fpga-mgr.txt(560 B)
📄 xlnx,zynqmp-pcap-fpga.txt(641 B)

Editing: altera-hps2fpga-bridge.txt

Altera FPGA/HPS Bridge Driver

Required properties:
- regs		: base address and size for AXI bridge module
- compatible	: Should contain one of:
		  "altr,socfpga-lwhps2fpga-bridge",
		  "altr,socfpga-hps2fpga-bridge", or
		  "altr,socfpga-fpga2hps-bridge"
- resets	: Phandle and reset specifier for this bridge's reset
- clocks	: Clocks used by this module.

See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.

Example:
	fpga_bridge0: fpga-bridge@ff400000 {
		compatible = "altr,socfpga-lwhps2fpga-bridge";
		reg = <0xff400000 0x100000>;
		resets = <&rst LWHPS2FPGA_RESET>;
		clocks = <&l4_main_clk>;
		bridge-enable = <0>;
	};

fpga_bridge1: fpga-bridge@ff500000 {
		compatible = "altr,socfpga-hps2fpga-bridge";
		reg = <0xff500000 0x10000>;
		resets = <&rst HPS2FPGA_RESET>;
		clocks = <&l4_main_clk>;
		bridge-enable = <1>;
	};

fpga_bridge2: fpga-bridge@ff600000 {
		compatible = "altr,socfpga-fpga2hps-bridge";
		reg = <0xff600000 0x100000>;
		resets = <&rst FPGA2HPS_RESET>;
		clocks = <&l4_main_clk>;
	};

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Editing: altera-hps2fpga-bridge.txt

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